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| IMPORTANT NOTICE Dear customer, As from August 2nd 2008, the wireless operations of NXP have moved to a new company, ST-NXP Wireless. As a result, the following changes are applicable to the attached document. Company name - NXP B.V. is replaced with ST-NXP Wireless. Copyright - the copyright notice at the bottom of each page "(c) NXP B.V. 200x. All rights reserved", shall now read: "(c) ST-NXP Wireless 200x - All rights reserved". Web site - http://www.nxp.com is replaced with http://www.stnwireless.com Contact information - the list of sales offices previously obtained by sending an email to salesaddresses@nxp.com , is now found at http://www.stnwireless.com under Contacts. If you have any questions related to the document, please contact our nearest sales office. Thank you for your cooperation and understanding. ST-NXP Wireless www.stnwireless.com ISP1582 Hi-Speed USB peripheral controller Rev. 07 -- 22 September 2008 Product data sheet 1. General description The ISP1582 is a cost-optimized and feature-optimized Hi-Speed Universal Serial Bus (USB) peripheral controller. It fully complies with Ref. 1 "Universal Serial Bus Specification Rev. 2.0", supporting data transfer at high-speed (480 Mbit/s) and full-speed (12 Mbit/s). The ISP1582 provides high-speed USB communication capacity to systems based on microcontrollers or microprocessors. It communicates with a microcontroller or microprocessor of a system through a high-speed general-purpose parallel interface. The ISP1582 supports automatic detection of Hi-Speed USB system operation. Original USB fall-back mode allows the device to remain operational under full-speed conditions. It is designed as a generic USB peripheral controller so that it can fit into all existing device classes, such as imaging class, mass storage devices, communication devices, printing devices and human interface devices. The internal generic Direct Memory Access (DMA) block allows easy integration into data streaming applications. The modular approach to implementing a USB peripheral controller allows the designer to select the optimum system microcontroller from the wide variety available. The ability to reuse existing architecture and firmware shortens the development time, eliminates risk and reduces cost. The result is fast and efficient development of the most cost-effective USB peripheral solution. The ISP1582 also incorporates features such as SoftConnect, a reduced frequency crystal oscillator, and integrated termination resistors. These features allow significant cost savings in system design and easy implementation of advanced USB functionality into PC peripherals. 2. Features I Complies fully with: N Ref. 1 "Universal Serial Bus Specification Rev. 2.0" N Most device class specifications N ACPI, OnNow and USB power management requirements I Supports data transfer at high-speed (480 Mbit/s) and full-speed (12 Mbit/s) I High performance USB peripheral controller with integrated Serial Interface Engine (SIE), Parallel Interface Engine (PIE), FIFO memory and data transceiver I Automatic Hi-Speed USB mode detection and Original USB fall-back mode I Supports sharing mode I Supports VBUS sensing I Supports Generic DMA (GDMA) slave mode NXP Semiconductors ISP1582 Hi-Speed USB peripheral controller I I I I I I I I I I I I I I I High-speed DMA interface Fully autonomous and multi-configuration DMA operation Seven IN endpoints, seven OUT endpoints, and a fixed control IN and OUT endpoint Integrated physical 8 kB of multi-configuration FIFO memory Endpoints with double buffering to increase throughput and ease real-time data transfer Bus-independent interface with most microcontrollers and microprocessors 12 MHz crystal oscillator with integrated PLL for low EMI Software-controlled connection to the USB bus (SoftConnect) Low-power consumption in operation and power-down modes; suitable for use in bus-powered USB devices Supports Session Request Protocol (SRP) that adheres to Ref. 2 "On-The-Go Supplement to the USB Specification Rev. 1.3" Internal power-on and low-voltage reset circuits; also supports software reset Operation over the extended USB bus voltage range (DP, DM and VBUS) 5 V tolerant I/O pads Operating temperature range from -40 C to +85 C Available in HVQFN56 halogen-free and lead-free package 3. Applications I I I I I I I I Personal digital assistant Digital video camera Digital still camera 3G mobile phone MP3 player Communication device, for example: router and modem Printer Scanner 4. Ordering information Table 1. Ordering information Package Name ISP1582BS HVQFN56 Description plastic thermal enhanced very thin quad flat package; no leads; 56 terminals; body 8 x 8 x 0.85 mm Version SOT684-1 Type number ISP1582_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 2 of 68 xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x Product data sheet Rev. 07 -- 22 September 2008 (c) NXP B.V. 2008. All rights reserved. ISP1582_7 5. Block diagram NXP Semiconductors 12 MHz to or from USB DP DM DREQ DACK DIOR DIOW VBUS XTAL1 XTAL2 51 9 3.3 V 1.5 k 3 4 49 52 10 11 12 8 EOT ISP1582 2 SoftConnect DMA HANDLER RPU DMA INTERFACE 30 to 33, 35 to 40, 42 to 47 16 RREF 12.0 k 6 HI-SPEED USB TRANSCEIVER NXP SIE/PIE MEMORY MANAGEMENT UNIT DMA REGISTERS 18 to 20, 22 to 25, 27 8 DATA [15:0] RESET_N 7 POWER-ON RESET internal reset INTEGRATED RAM (8 kB) MICROCONTROLLER HANDLER MICROCONTROLLER INTERFACE A[7:0] 15 16 CS_N RD_N WR_N INT analog supply 17 digital supply SYSTEM CONTROLLER I/O pad supply OTG SRP MODULE 14 VCC 53, 54 3.3 V VOLTAGE REGULATORS Hi-Speed USB peripheral controller 13, 26, 29, 41 1, 5 28, 50 VCC1V8 56 55 21, 34, 48 004aaa199 DGND AGND SUSPEND WAKEUP VCC(I/O) ISP1582 3 of 68 Fig 1. Block diagram NXP Semiconductors ISP1582 Hi-Speed USB peripheral controller 6. Pinning information 6.1 Pinning 56 SUSPEND 55 WAKEUP 50 VCC1V8 47 DATA15 46 DATA14 45 DATA13 44 DATA12 terminal 1 index area AGND RPU DP DM AGND RREF RESET_N EOT DREQ 1 2 3 4 5 6 7 8 9 43 DATA11 42 DATA10 41 DGND 40 DATA9 39 DATA8 38 DATA7 37 DATA6 36 DATA5 35 DATA4 34 VCC(I/O) 33 DATA3 32 DATA2 31 DATA1 30 DATA0 29 DGND VCC1V8 28 004aaa536 ISP1582BS DACK 10 DIOR 11 DIOW 12 DGND 13 INT 14 CS_N 15 RD_N 16 WR_N 17 A0 18 A1 19 A2 20 VCC(I/O) 21 A3 22 A4 23 A5 24 A6 25 DGND 26 A7 27 Transparent top view Fig 2. Pin configuration HVQFN56 (top view) 6.2 Pin description Table 2. Symbol[1] AGND RPU Pin description Pin 1 2 Type[2] A Description analog ground pull-up resistor connection; connect to the external pull-up resistor for pin DP; must be connected to 3.3 V through a 1.5 k resistor USB D+ line connection (analog) USB D- line connection (analog) analog ground external bias resistor connection; connect to the external bias resistor; must be connected to ground through a 12.0 k 1 % resistor DP DM AGND RREF 3 4 5 6 A A A ISP1582_7 48 VCC(I/O) 52 XTAL1 51 XTAL2 49 VBUS 54 VCC 53 VCC (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 4 of 68 NXP Semiconductors ISP1582 Hi-Speed USB peripheral controller Pin description ...continued Pin 7 Type[2] I Description reset input (500 s); a LOW level produces an asynchronous reset; connect to VCC for power-on reset (internal POR circuit) When the RESET_N pin is LOW, ensure that the WAKEUP pin does not go from LOW to HIGH; otherwise the device will enter test mode. TTL; 5 V tolerant Table 2. Symbol[1] RESET_N EOT 8 I end-of-transfer input (programmable polarity); when not in use, connect this pin to VCC(I/O) through a 10 k resistor input pad; TTL; 5 V tolerant DMA request (programmable polarity) output; when not in use, connect this pin to ground through a 10 k resistor; see Table 51 and Table 52 TTL; 4 ns slew-rate control DMA acknowledge input (programmable polarity); when not in use, connect this pin to VCC(I/O) through a 10 k resistor; see Table 51 and Table 52 TTL; 5 V tolerant DMA read strobe input (programmable polarity); when not in use, connect this pin to VCC(I/O) through a 10 k resistor; see Table 51 and Table 52 TTL; 5 V tolerant DMA write strobe input (programmable polarity); when not in use, connect this pin to VCC(I/O) through a 10 k resistor; see Table 51 and Table 52 TTL; 5 V tolerant digital ground interrupt output; programmable polarity (active HIGH or LOW) and signaling (edge or level triggered) CMOS output; 8 mA drive chip select input input pad; TTL; 5 V tolerant read strobe input input pad; TTL; 5 V tolerant write strobe input input pad; TTL; 5 V tolerant bit 0 of the address bus input pad; TTL; 5 V tolerant bit 1 of the address bus input pad; TTL; 5 V tolerant bit 2 of the address bus input pad; TTL; 5 V tolerant supply voltage; used to supply voltage to the I/O pads; see Section 7.15 bit 3 of the address bus input pad; TTL; 5 V tolerant DREQ 9 O DACK 10 I DIOR 11 I DIOW 12 I DGND INT 13 14 O CS_N RD_N WR_N A0 A1 A2 VCC(I/O) A3 [3] 15 16 17 18 19 20 21 22 I I I I I I I ISP1582_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 5 of 68 NXP Semiconductors ISP1582 Hi-Speed USB peripheral controller Pin description ...continued Pin 23 24 25 26 27 28 Type[2] I I I I Description bit 4 of the address bus input pad; TTL; 5 V tolerant bit 5 of the address bus input pad; TTL; 5 V tolerant bit 6 of the address bus input pad; TTL; 5 V tolerant digital ground bit 7 of the address bus input pad; TTL; 5 V tolerant regulator output voltage (1.8 V 0.15 V); tapped out voltage from the internal regulator; this regulated voltage cannot drive external devices; decouple this pin using a 0.1 F capacitor; see Section 7.15 digital ground bit 0 of bidirectional data bus bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant bit 1 of bidirectional data bus bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant bit 2 of bidirectional data bus bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant bit 3 of bidirectional data bus bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant supply voltage; used to supply voltage to the I/O pads; see Section 7.15 bit 4 of bidirectional data bus bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant bit 5 of bidirectional data bus bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant bit 6 of bidirectional data bus bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant bit 7 of bidirectional data bus bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant bit 8 of bidirectional data bus bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant bit 9 of bidirectional data bus bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant digital ground bit 10 of bidirectional data bus bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant bit 11 of bidirectional data bus bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant bit 12 of bidirectional data bus bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant Table 2. Symbol[1] A4 A5 A6 DGND A7 VCC1V8[3] DGND DATA0 DATA1 DATA2 DATA3 VCC(I/O) DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DGND DATA10 DATA11 DATA12 [3] 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O ISP1582_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 6 of 68 NXP Semiconductors ISP1582 Hi-Speed USB peripheral controller Pin description ...continued Pin 45 46 47 48 49 Type[2] I/O I/O I/O A Description bit 13 of bidirectional data bus bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant bit 14 of bidirectional data bus bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant bit 15 of bidirectional data bus bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant supply voltage; used to supply voltage to the I/O pads; see Section 7.15 USB bus power sensing input -- Used to detect whether the host is connected or not; connect a 1 F electrolytic or tantalum capacitor, and a 1 M pull-down resistor to ground; see Section 7.13 VBUS pulsing output -- In OTG mode; connect a 1 F electrolytic or tantalum capacitor, and a 1 M pull-down resistor to ground; see Section 7.13 5 V tolerant Table 2. Symbol[1] DATA13 DATA14 DATA15 VCC(I/O) VBUS [3] VCC1V8[3] 50 - voltage regulator output (1.8 V 0.15 V); tapped out voltage from the internal regulator; this regulated voltage cannot drive external devices; decouple this pin using 4.7 F and 0.1 F capacitors; see Section 7.15 crystal oscillator output (12 MHz); connect a fundamental parallel-resonant crystal; leave this pin open when using an external clock source on pin XTAL1; see Table 79 crystal oscillator input (12 MHz); connect a fundamental parallel-resonant crystal or an external clock source (leaving pin XTAL2 unconnected); see Table 79 supply voltage (3.3 V 0.3 V); this pin supplies the internal voltage regulator and the analog circuit; see Section 7.15 supply voltage (3.3 V 0.3 V); this pin supplies the internal voltage regulator and the analog circuit; see Section 7.15 wake-up input; when this pin is at the HIGH level, the chip is prevented from getting into the suspend state and wake-up the chip when already in suspend mode; when not in use, connect this pin to ground through a 10 k resistor When the RESET_N pin is LOW, ensure that the WAKEUP pin does not go from LOW to HIGH; otherwise the device will enter test mode. input pad; TTL; 5 V tolerant XTAL2 51 O XTAL1 52 I VCC[3] VCC[3] WAKEUP 53 54 55 I SUSPEND 56 O suspend state indicator output; used as a power switch control output to power-off or power-on external devices when going into suspend mode or recovering from suspend mode CMOS output; 8 mA drive ground supply; down bonded to the exposed die pad (heat sink); to be connected to DGND during PCB layout GND exposed die pad - [1] [2] [3] Symbol names ending with underscore N (for example, NAME_N) represent active LOW signals. All outputs and I/O pins can source 4 mA, unless otherwise specified. Add a decoupling capacitor (0.1 F) to all the supply pins. For better EMI results, add a 0.01 F capacitor in parallel to the 0.1 F. (c) NXP B.V. 2008. All rights reserved. ISP1582_7 Product data sheet Rev. 07 -- 22 September 2008 7 of 68 NXP Semiconductors ISP1582 Hi-Speed USB peripheral controller 7. Functional description The ISP1582 is a high-speed USB peripheral controller. It implements the Hi-Speed USB or the Original USB physical layer, and the packet protocol layer. It concurrently maintains up to 16 USB endpoints (control IN, control OUT, and seven IN and seven OUT configurable) along with endpoint EP0 setup, which accesses the set-up buffer. The Ref. 1 "Universal Serial Bus Specification Rev. 2.0", Chapter 9 protocol handling is executed using the external firmware. For high-bandwidth data transfer, the integrated DMA handler can be invoked to transfer data to or from external memory or devices. The DMA interface can be configured by writing to proper DMA registers (see Section 8.4). The ISP1582 supports Hi-Speed USB and Original USB signaling. The USB signaling speed is automatically detected. The ISP1582 has 8 kB of internal FIFO memory, which is shared among enabled USB endpoints, including control IN and control OUT endpoints, and set-up token buffer. There are seven IN and seven OUT configurable endpoints, and two fixed control endpoints that are 64 bytes long. Any of the seven IN and seven OUT endpoints can be separately enabled or disabled. The endpoint type (interrupt, isochronous or bulk) and packet size of these endpoints can be individually configured, depending on the requirements of the application. Optional double buffering increases the data throughput of these data endpoints. The ISP1582 requires 3.3 V power supply. It has 5 V tolerant I/O pads and an internal 1.8 V regulator to power the digital logic. Table 3. Endpoint identifier EP0SETUP EP0RX EP0TX EP1RX EP1TX EP2RX EP2TX EP3RX EP3TX EP4RX EP4TX EP5RX EP5TX EP6RX EP6TX EP7RX EP7TX ISP1582_7 Endpoint access and programmability Maximum packet size 8 bytes (fixed) 64 bytes (fixed) 64 bytes (fixed) programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable Double buffering Endpoint type no no no yes yes yes yes yes yes yes yes yes yes yes yes yes yes set-up token control OUT control IN programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable Direction OUT OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 8 of 68 NXP Semiconductors ISP1582 Hi-Speed USB peripheral controller The ISP1582 operates on a 12 MHz crystal oscillator. An integrated 40 x PLL clock multiplier generates the internal sampling clock of 480 MHz. 7.1 DMA interface, DMA handler and DMA registers The DMA block can be subdivided into two blocks: DMA handler and DMA interface. The firmware writes to the DMA Command register to start a DMA transfer (see Table 44). The handler interfaces to the same FIFO (internal RAM) as used by the USB core. On receiving the DMA command, the DMA handler directs the data from the endpoint FIFO to the external DMA device or from the external DMA device to the endpoint FIFO. The DMA interface configures the timing and the DMA handshake. Data can be transferred using either the DIOR and DIOW strobes or by the DACK and DREQ handshakes. DMA configurations are set up by writing to the DMA Configuration register (see Table 49 and Table 50). Remark: The DMA endpoint buffer length must be a multiple of 4 bytes. For details on DMA registers, see Section 8.4. 7.2 Hi-Speed USB transceiver The analog transceiver directly interfaces to the USB cable through integrated termination resistors. The high-speed transceiver requires an external resistor (12.0 k 1 %) between pin RREF and ground to ensure an accurate current mirror that generates the Hi-Speed USB current drive. A full-speed transceiver is integrated as well. This makes the ISP1582 compliant to Hi-Speed USB and Original USB, supporting both the high-speed and full-speed physical layers. After automatic speed detection, the NXP Serial Interface Engine (SIE) sets the transceiver to use either high-speed or full-speed signaling. 7.3 MMU and integrated RAM The Memory Management Unit (MMU) manages the access to the integrated RAM that is shared by the USB, microcontroller handler and DMA handler. Data from the USB bus is stored in the integrated RAM, which is cleared only when the microcontroller has read the corresponding endpoint, or the DMA controller has written all data from the RAM of the corresponding endpoint to the DMA bus. The OUT endpoint buffer can also be forcibly cleared by setting bit CLBUF in the Control Function register. A total of 8 kB RAM is available for buffering. 7.4 Microcontroller interface and microcontroller handler The microcontroller handler allows the external microcontroller or microprocessor to access the register set in the NXP SIE, as well as the DMA handler. The initialization of the DMA configuration is done through the microcontroller handler. 7.5 OTG SRP module The OTG supplement defines a Session Request Protocol (SRP), which allows a B-device to request the A-device to turn on VBUS and start a session. This protocol allows the A-device, which may be battery-powered, to conserve power by turning off VBUS when there is no bus activity while still providing a means for the B-device to initiate bus activity. ISP1582_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 9 of 68 NXP Semiconductors ISP1582 Hi-Speed USB peripheral controller Any A-device, including a PC or laptop, can respond to SRP. Any B-device, including a standard USB peripheral, can initiate SRP. The ISP1582 is a device that can initiate SRP. 7.6 NXP high-speed transceiver 7.6.1 NXP Parallel Interface Engine (PIE) In the High-Speed (HS) transceiver, the NXP PIE interface uses a 16-bit parallel bidirectional data interface. The functions of the HS module also include bit-stuffing or de-stuffing and Non-Return-to-Zero Inverted (NRZI) encoding or decoding logic. 7.6.2 Peripheral circuit To maintain a constant current driver for HS transmit circuits and to bias other analog circuits, an internal band gap reference circuit and an RREF resistor form the reference current. This circuit requires an external precision resistor (12.0 k 1 %) connected to the analog ground. 7.6.3 HS detection The ISP1582 handles more than one electrical state, Full-Speed (FS) or High-Speed (HS), under the USB specification. When the USB cable is connected from the peripheral to the host controller, the ISP1582 defaults to the FS state, until it sees a bus reset from the host controller. During the bus reset, the peripheral initiates an HS chirp to detect whether the host controller supports Hi-Speed USB or Original USB. If the HS handshake shows that there is an HS host connected, then the ISP1582 switches to the HS state. In the HS state, the ISP1582 must observe the bus for periodic activity. If the bus remains inactive for 3 ms, the peripheral switches to the FS state to check for a Single-Ended Zero (SE0) condition on the USB bus. If an SE0 condition is detected for the designated time (100 s to 875 s; refer to Ref. 1 "Universal Serial Bus Specification Rev. 2.0", Section 7.1.7.6), the ISP1582 switches to the HS chirp state to perform an HS detection handshake. Otherwise, the ISP1582 remains in the FS state, adhering to the bus-suspend specification. 7.6.4 Isolation Ensure that the DP and DM lines are maintained in a clean state, without any residual voltage or glitches. Once the ISP1582 is reset and the clock is available, ensure that there are no erroneous pulses or glitches even of very small amplitude on the DP and DM lines. Remark: If there are any erroneous unwanted pulses or glitches detected by the ISP1582 DP and DM lines, there is a possibility of the ISP1582 clocking this state into the internal core, causing unknown behaviors. ISP1582_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 10 of 68 NXP Semiconductors ISP1582 Hi-Speed USB peripheral controller 7.7 NXP Serial Interface Engine (SIE) The NXP SIE implements the full USB protocol layer. It is completely hardwired for speed and needs no firmware intervention. The functions of this block include: synchronization pattern recognition, parallel or serial conversion, bit-stuffing or de-stuffing, CRC checking or generation, Packet IDentifier (PID) verification or generation, address recognition, handshake evaluation or generation. 7.8 SoftConnect The USB connection is established by pulling pin DP (for full-speed devices) to HIGH through a 1.5 k pull-up resistor. In the ISP1582, an external 1.5 k pull-up resistor must be connected between pin RPU and 3.3 V. Pin RPU connects the pull-up resistor to pin DP, when bit SOFTCT in the Mode register is set (see Table 18 and Table 19). After a hardware reset, the pull-up resistor is disconnected by default (bit SOFTCT = 0). The USB bus reset does not change the value of bit SOFTCT. When VBUS is not present, the SOFTCT bit must be set to logic 0 to comply with the back-drive voltage. 7.9 Reconfiguring endpoints The ISP1582 endpoints have a limitation when implementing a composite device with at least two functionalities that require the support of alternate settings, for example, the video class and audio class devices. The ISP1582 endpoints cannot be reconfigured on the fly because it is implemented as a FIFO base. The internal RAM partition will be corrupted if there is a need to reconfigure endpoints on the fly because of alternate settings request, causing data corruption. For details and workaround, refer to Ref. 3 "Using ISP1582/3 in a composite device application with alternate settings (AN10071)". 7.10 System controller The system controller implements the USB power-down capabilities of the ISP1582. Registers are protected against data corruption during wake-up following a resume (from the suspend state) by locking the write access, until an unlock code is written in the Unlock Device register (see Table 69 and Table 70). 7.11 Pins status Table 4 illustrates the behavior of ISP1582 pins with VCC(I/O) and VCC in various operating conditions. Table 4. VCC 0V ISP1582 pin status Pin Input 0V dead[1] reset unknown 3.3 V VCC 3.3 V VCC Output unknown I/O unknown high-Z state depends on how the pin is configured VCC(I/O) State state depends on how the pin is driven output after reset state depends on how the pin is driven output [1] Dead: The USB cable is plugged out, and VCC(I/O) is not available. (c) NXP B.V. 2008. All rights reserved. ISP1582_7 Product data sheet Rev. 07 -- 22 September 2008 11 of 68 NXP Semiconductors ISP1582 Hi-Speed USB peripheral controller Table 5 illustrates the behavior of output pins with VCC(I/O) and VCC in various operating conditions. Table 5. VCC 0V 3.3 V 3.3 V [1] [2] ISP1582 output status VCC(I/O) 0V VCC VCC State dead[1] reset after reset INT X[2] HIGH HIGH SUSPEND X[2] LOW LOW Dead: The USB cable is plugged out, and VCC(I/O) is not available. X: Don't care. 7.12 Interrupt 7.12.1 Interrupt output pin The Interrupt Configuration register of the ISP1582 controls the behavior of the INT output pin. The polarity and signaling mode of pin INT can be programmed by setting bits INTPOL and INTLVL of the Interrupt Configuration register (R/W: 10h); see Table 22. Bit GLINTENA of the Mode register (R/W: 0Ch) is used to enable pin INT. Default settings after reset are active LOW and level mode. When pulse mode is selected, a pulse of 60 ns is generated when the OR-ed combination of all interrupt bits changes from logic 0 to logic 1. Figure 3 shows the relationship between interrupt events and pin INT. Each of the indicated USB and DMA events is logged in a status bit of the Interrupt register and the DMA Interrupt Reason register, respectively. Corresponding bits in the Interrupt Enable register and the DMA Interrupt Enable register determine whether an event will generate an interrupt. Interrupts can be masked globally by means of bit GLINTENA of the Mode register; see Table 19. Field CDBGMOD[1:0] of the Interrupt Configuration register controls the generation of INT signals for the control pipe. Field DDBGMODIN[1:0] of the Interrupt Configuration register controls the generation of INT signals for the IN pipe. Field DDBGMODOUT[1:0] of the Interrupt Configuration register controls the generation of INT signals for the OUT pipe; see Table 23. ISP1582_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 12 of 68 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Product data sheet Rev. 07 -- 22 September 2008 (c) NXP B.V. 2008. All rights reserved. ISP1582_7 NXP Semiconductors DMA Interrupt Reason register EXT_EOT INT_EOT DMA_XFER_OK Interrupt Enable register IEBRESET IESOF .... IEDMA DMA Interrupt Enable register IE_EXT_EOT ...... .... OR IE_INT_EOT IE_DMA_XFER_OK IEP7RX IEP7TX OR Interrupt register BRESET SOF ...... .... DMA INT ...... EP7RX EP7TX 004aaa275 LE LATCH Interrupt Configuration register PULSE OR LEVEL GENERATOR INTPOL Mode register GLINTENA Hi-Speed USB peripheral controller ISP1582 13 of 68 Fig 3. Interrupt logic NXP Semiconductors ISP1582 Hi-Speed USB peripheral controller 7.12.2 Interrupt control Bit GLINTENA in the Mode register is a global interrupt enable or disable bit. The behavior of this bit is given in Figure 4. The following illustrations are only applicable for level trigger. Event A: When an interrupt event occurs (for example, SOF interrupt) with bit GLINTENA set to logic 0, an interrupt will not be generated at pin INT. It will, however, be registered in the corresponding Interrupt register bit. Event B: When bit GLINTENA is set to logic 1, pin INT is asserted because bit SOF in the Interrupt register is already set. Event C: If the firmware sets bit GLINTENA to logic 0, pin INT will still be asserted. The bold line shows the desired behavior of pin INT. Deassertion of pin INT can be achieved either by clearing all the bits in the Interrupt register or the DMA Interrupt Reason register, depending on the event. Remark: When clearing an interrupt event, perform write to all the bytes of the register. For more information on interrupt control, see Section 8.2.2, Section 8.2.5 and Section 8.5.1. A INT pin B C GLINTENA = 0 (during this time, an interrupt event occurs, for example, SOF asserted) GLINTENA = 1 SOF asserted GLINTENA = 0 SOF asserted 004aaa394 Pin INT: HIGH = deassert; LOW = assert (individual interrupts are enabled). Fig 4. Behavior of bit GLINTENA 7.13 VBUS sensing The VBUS pin is one of the ways to wake up the clock when the ISP1582 is suspended with bit CLKAON set to logic 0 (clock off option). To detect whether the host is connected or not, that is VBUS sensing, a 1 M resistor and a 1 F electrolytic or tantalum capacitor must be added to damp the overshoot on plug-in. ISP1582_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 14 of 68 NXP Semiconductors ISP1582 Hi-Speed USB peripheral controller 49 ISP1582 1 M 1 F USB CONNECTOR 004aaa440 Fig 5. Resistor and electrolytic or tantalum capacitor needed for VBUS sensing 001aaf440 Fig 6. Oscilloscope reading: no resistor and capacitor in the network 001aaf441 Fig 7. Oscilloscope reading: with resistor and capacitor in the network 7.14 Power-on reset The ISP1582 requires a minimum pulse width of 500 s. ISP1582_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 15 of 68 NXP Semiconductors ISP1582 Hi-Speed USB peripheral controller The RESET_N pin can either be connected to VCC (using the internal POR circuit) or externally controlled (by the microcontroller, ASIC, and so on). When VCC is directly connected to the RESET_N pin, the internal pulse width tPORP will typically be 200 ns. The power-on reset function can be explained by viewing the dips at t2 to t3 and t4 to t5 on the VCC(POR) curve (Figure 8). t0 -- The internal POR starts with a HIGH level. t1 -- The detector will see the passing of the trip level and a delay element will add another tPORP before it drops to LOW. t2-t3 -- The internal POR pulse will be generated whenever VCC(POR) drops below Vtrip for more than 11 s. t4-t5 -- The dip is too short (< 11 s) and the internal POR pulse will not react and will remain LOW. VCC(POR) Vtrip t0 t1 t2 t3 t4 t5 PORP(1) 004aab162 tPORP tPORP (1) PORP = Power-On Reset Pulse. Fig 8. POR timing Figure 9 shows the availability of the clock with respect to the external POR. VCC 500 s external clock 2 ms RESET_N A B C 004aaa927 Power on VCC at A. Stable external clock is to be available at B. The ISP1582 is operational at C. Fig 9. Clock with respect to the external POR 7.15 Power supply The ISP1582 can be powered by 3.3 V 0.3 V. For connection details, see Figure 10. If the ISP1582 is powered by VCC = 3.3 V, an integrated 3.3 V-to-1.8 V voltage regulator provides a 1.8 V supply voltage for the internal logic. ISP1582_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 16 of 68 NXP Semiconductors ISP1582 Hi-Speed USB peripheral controller 53, 54 VCC 0.01 F 3.3 V 0.3 V 0.1 F 48 VCC(I/O) 0.01 F 0.1 F VCC 34 VCC(I/O) 0.01 F 0.1 F ISP1582 21 VCC(I/O) 0.01 F 0.1 F 50 VCC1V8 4.7 F(1) 0.1 F 28 VCC1V8 0.1 F 004aaa203 (1) At the VCC input (3.3 V) to the USB controller, if the ripple voltage is less than 20 mV, then 4.7 F standard electrolytic or tantalum capacitors (tested ESR up to 10 ) should be OK at the VCC1V8 output. If the ripple voltage at the input is higher than 20 mV, then use 4.7 F LOW ESR capacitors (ESR from 0.2 to 2 ) at the VCC1V8 output. This is to improve the high-speed signal quality at the USB side. Fig 10. ISP1582 with 3.3 V supply Table 6 shows power modes in which the ISP1582 can be operated. Table 6. VCC VBUS [1] Power modes VCC(I/O) VBUS [2] Power mode bus-powered self-powered System-powered [1] [2] system-powered The power supply to the IC (VCC) is 3.3 V. Therefore, if the application is bus-powered, a 3.3 V regulator must be used. VCC(I/O) = VCC. If the application is bus-powered, a voltage regulator must be used. ISP1582_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 17 of 68 NXP Semiconductors ISP1582 Hi-Speed USB peripheral controller 7.15.1 Self-powered mode 1.5 k RPU VCC VBUS VBUS USB ISP1582 1 F 1 M VCC(I/O) 004aaa460 VCC(I/O) and VCC are system powered. Fig 11. Self-powered mode In self-powered mode, VCC and VCC(I/O) are supplied by the system. See Figure 11. Table 7. Operation truth table for SoftConnect Power supply VCC Normal bus operation No pull-up on DP [1] ISP1582 operation VCC(I/O) 3.3 V 3.3 V RPU (3.3 V) 3.3 V 3.3 V VBUS 5V 0 V[1] Bit SOFTCT in Mode register enabled disabled 3.3 V 3.3 V When the USB cable is removed, SoftConnect is disabled. Table 8. Operation truth table for clock off during suspend Power supply VCC VCC(I/O) 3.3 V RPU (3.3 V) 3.3 V VBUS 5V Clock off during suspend enabled ISP1582 operation Clock will wake up: After resume and After a bus reset Clock will wake up: After detecting the presence of VBUS Table 9. 3.3 V 3.3 V 3.3 V 3.3 V 0V5V enabled Operation truth table for back voltage compliance Power supply VCC VCC(I/O) 3.3 V 3.3 V RPU (3.3 V) 3.3 V 3.3 V VBUS 5V 0V Bit SOFTCT in Mode register enabled disabled ISP1582 operation Back voltage is not measured in this mode 3.3 V Back voltage is not an issue because pull 3.3 V up on DP will not be present when VBUS is not present ISP1582_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 18 of 68 NXP Semiconductors ISP1582 Hi-Speed USB peripheral controller Operation truth table for OTG Power supply VCC VCC(I/O) 3.3 V 3.3 V RPU (3.3 V) 3.3 V 3.3 V VBUS 5V 0V not applicable operational OTG register Table 10. ISP1582 operation SRP is not applicable SRP is possible 3.3 V 3.3 V 7.15.2 Bus-powered mode 5 V-to-3.3 V VOLTAGE REGULATOR VBUS VCC VBUS USB 3.3 V ISP1582 VCC(I/O) 1.5 k 1 F 1 M RPU 004aaa462 VCC(I/O) is powered by VBUS. Fig 12. Bus-powered mode In bus-powered mode (see Figure 12), VCC and VCC(I/O) are supplied by the output of the 5 V-to-3.3 V voltage regulator. The input to the regulator is from VBUS. On plugging the USB cable, the ISP1582 goes through the power-on reset cycle. In this mode, OTG is disabled. Table 11. Operation truth table for SoftConnect Power supply VCC Normal bus operation Power loss Table 12. 3.3 V 0V VCC(I/O) 3.3 V 0V RPU (3.3 V) 3.3 V 0V VBUS 5V 0V Bit SOFTCT in Mode register enabled not applicable ISP1582 operation Operation truth table for clock off during suspend Power supply VCC VCC(I/O) 3.3 V RPU (3.3 V) 3.3 V VBUS 5V Clock off during suspend enabled ISP1582 operation Clock will wake up: After resume and After a bus reset Power loss 3.3 V 0V 0V 0V 0V not applicable ISP1582_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 19 of 68 NXP Semiconductors ISP1582 Hi-Speed USB peripheral controller Operation truth table for back voltage compliance Power supply VCC VCC(I/O) 3.3 V 0V RPU (3.3 V) 3.3 V 0V VBUS 5V 0V Bit SOFTCT in Mode register enabled not applicable Table 13. ISP1582 operation Back voltage is not measured in this mode Power loss Table 14. 3.3 V 0V Operation truth table for OTG Power supply VCC VCC(I/O) 3.3 V 0V RPU (3.3 V) 3.3 V 0V VBUS 5V 0V not applicable not applicable OTG register ISP1582 operation SRP is not applicable Power loss 3.3 V 0V ISP1582_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 20 of 68 NXP Semiconductors ISP1582 Hi-Speed USB peripheral controller 8. Register description Table 15. Name Initialization registers Address Mode Interrupt Configuration OTG Interrupt Enable Data flow registers Endpoint Index Control Function Data Port Buffer Length Buffer Status Endpoint MaxPacketSize Endpoint Type DMA registers DMA Command DMA Transfer Counter DMA Configuration DMA Hardware DMA Interrupt Reason DMA Interrupt Enable DMA Endpoint DMA Burst Counter DMA controller DMA controller DMA controller DMA controller DMA controller DMA controller DMA controller DMA controller 30h 34h 38h 3Ch 50h 54h 58h 64h controls all DMA transfers sets byte count for DMA transfer sets GDMA configuration (counter enable, data strobing, bus width) endian type, signal polarity for DACK, DREQ, DIOW, DIOR, EOT 1 4 2 1 Section 8.4.1 on page 37 Section 8.4.2 on page 38 Section 8.4.3 on page 39 Section 8.4.4 on page 40 Section 8.4.5 on page 41 Section 8.4.6 on page 42 Section 8.4.7 on page 43 Section 8.4.8 on page 43 (c) NXP B.V. 2008. All rights reserved. Register overview Destination Address Description Size (bytes) 1 2 1 1 4 Reference device device device device device 00h 0Ch 10h 12h 14h USB device address and enable power-down options, global interrupt enable, SoftConnect interrupt sources, trigger mode, output polarity OTG implementation interrupt source enabling Section 8.2.1 on page 22 Section 8.2.2 on page 23 Section 8.2.3 on page 24 Section 8.2.4 on page 25 Section 8.2.5 on page 27 Section 8.3.1 on page 29 Section 8.3.2 on page 30 Section 8.3.3 on page 31 Section 8.3.4 on page 32 Section 8.3.5 on page 33 Section 8.3.6 on page 34 Section 8.3.7 on page 35 endpoints endpoint endpoint endpoint endpoint endpoint endpoint 2Ch 28h 20h 1Ch 1Eh 04h 08h endpoint selection, data flow direction endpoint buffer management data access to endpoint FIFO packet size counter buffer status for each endpoint maximum packet size selects endpoint type: isochronous, bulk or interrupt 1 1 2 2 1 2 2 shows reason (source) for DMA interrupt 2 enables DMA interrupt sources 2 selects endpoint FIFO, data flow direction 1 DMA burst counter 2 ISP1582_7 Product data sheet Rev. 07 -- 22 September 2008 21 of 68 NXP Semiconductors ISP1582 Hi-Speed USB peripheral controller Table 15. Name Register overview ...continued Destination Address Description Size (bytes) 4 3 2 Reference General registers Interrupt Chip ID Frame Number device device device 18h 70h 74h shows interrupt sources product ID code and hardware version last successfully received Start-Of-Frame: lower byte (byte 0) is accessed first allows save or restore of firmware status during suspend re-enables register write access after suspend direct setting of the DP and DM states, internal transceiver test (PHY) Section 8.5.1 on page 44 Section 8.5.2 on page 46 Section 8.5.3 on page 46 Section 8.5.4 on page 47 Section 8.5.5 on page 47 Section 8.5.6 on page 48 Scratch Unlock Device Test Mode device device PHY 78h 7Ch 84h 2 2 1 8.1 Register access The ISP1582 uses a 16-bit bus access. For single-byte registers, the upper byte (MSByte) must be ignored. Endpoint specific registers are indexed using the Endpoint Index register. The target endpoint must be selected before accessing the following registers: * * * * * * Buffer length Buffer status Control function Data port Endpoint MaxPacketSize Endpoint type Remark: Write zero to all reserved bits, unless otherwise specified. 8.2 Initialization registers 8.2.1 Address register (address: 00h) This register sets the USB assigned address and enables the USB device. Table 16 shows the Address register bit allocation. Bits DEVADDR[6:0] will be cleared whenever a bus reset, a power-on reset or a soft reset occurs. Bit DEVEN will be cleared whenever a power-on reset or a soft reset occurs. In response to the standard USB request SET_ADDRESS, firmware must write the (enabled) device address to the Address register, followed by sending an empty packet to the host. The new device address is activated when the device receives an acknowledgment from the host for the empty packet token. ISP1582_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 22 of 68 NXP Semiconductors ISP1582 Hi-Speed USB peripheral controller Table 16. Bit Symbol Reset Bus reset Access Address register: bit allocation 7 DEVEN 0 unchanged R/W 0 0 R/W Table 17. Bit 7 0 0 R/W 0 0 R/W 6 5 4 3 DEVADDR[6:0] 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W 2 1 0 Address register: bit description Description Device Enable: Logic 1 enables the device. The device will not respond to the host, unless this bit is set. Device Address: This field specifies the USB device address. Symbol DEVEN 6 to 0 DEVADDR [6:0] 8.2.2 Mode register (address: 0Ch) This register consists of 2 bytes (bit allocation: see Table 18). The Mode register controls resume, suspend and wake-up behavior, interrupt activity, soft reset, clock signals and SoftConnect operation. Table 18. Bit Symbol Reset Bus reset Access Bit Symbol Reset Bus reset Access [1] Mode register: bit allocation 15 14 13 reserved R 7 CLKAON 0 unchanged R/W R 6 SNDRSU 0 0 R/W R 5 GOSUSP 0 0 R/W R 4 SFRESET 0 0 R/W R 3 GLINTENA 0 unchanged R/W R 2 WKUPCS 0 0 R/W 12 11 10 9 DMA CLKON 0 0 R/W 1 PWRON 0 unchanged R/W 8 VBUSSTAT -[1] -[1] R 0 SOFTCT 0 unchanged R/W Value depends on the status of the VBUS pin. Table 19. Bit 15 to 10 9 Mode register: bit description Symbol DMACLKON Description reserved DMA Clock On: 0 -- Power save mode; the DMA circuit will stop completely to save power. 1 -- Supply clock to the DMA circuit. 8 VBUSSTAT VBUS Pin Status: This bit reflects the VBUS pin status. ISP1582_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 23 of 68 NXP Semiconductors ISP1582 Hi-Speed USB peripheral controller Mode register: bit description ...continued Symbol CLKAON Description Clock Always On: Logic 1 indicates that internal clocks are always running when in the suspend state. Logic 0 switches off the internal oscillator and PLL when the device goes into suspend mode. The device will consume less power if this bit is set to logic 0. The clock is stopped about 2 ms after bit GOSUSP is set and then cleared. Send Resume: Writing logic 1, followed by logic 0 will generate a 10 ms upstream resume signal. Remark: The upstream resume signal is generated 5 ms after this bit is set to logic 0. Table 19. Bit 7 6 SNDRSU 5 4 GOSUSP SFRESET Go Suspend: Writing logic 1, followed by logic 0 will activate suspend mode. Soft Reset: Writing logic 1, followed by logic 0 will enable a software-initiated reset to the ISP1582. A soft reset is similar to a hardware-initiated reset (using pin RESET_N). Global Interrupt Enable: Logic 1 enables all interrupts. Individual interrupts can be masked by clearing the corresponding bits in the Interrupt Enable register. When this bit is not set, an unmasked interrupt will not generate an interrupt trigger on the interrupt pin. If global interrupt, however, is enabled while there is any pending unmasked interrupt, an interrupt signal will be immediately generated on the interrupt pin. (If the interrupt is set to pulse mode, the interrupt events that were generated before the global interrupt is enabled will not appear on the interrupt pin). 3 GLINTENA 2 WKUPCS Wake Up On Chip Select: Logic 1 enables wake-up from suspend mode through a valid register read on the ISP1582. (A read will invoke the chip clock to restart. If you write to the register before the clock gets stable, it may cause malfunctioning). Power On: The SUSPEND pin output control. 0 -- The SUSPEND pin is HIGH when the ISP1582 is in the suspend state. Otherwise, the SUSPEND pin is LOW. 1 -- When the device is woken up from the suspend state, there will be a 1 ms active HIGH pulse on the SUSPEND pin. The SUSPEND pin will remain LOW in all other states. 1 PWRON 0 SOFTCT SoftConnect: Logic 1 enables the connection of the 1.5 k pull-up resistor on pin RPU to the DP pin. The status of the chip is shown in Table 20. Table 20. VBUS On Off Status of the chip SoftConnect = off pull-up resistor on pin DP is removed; suspend interrupt is generated after 3 ms of no bus activity pull-up resistor on pin DP is removed; suspend interrupt is generated after 3 ms of no bus activity SoftConnect = on pull-up resistor on pin DP pull-up resistor on pin DP is present; suspend interrupt is generated after 3 ms of no bus activity 8.2.3 Interrupt Configuration register (address: 10h) This 1-byte register determines the behavior and polarity of the INT output. The bit allocation is shown in Table 21. When the USB SIE receives or generates an ACK, NAK or NYET, it will generate interrupts, depending on three Debug mode fields. ISP1582_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 24 of 68 NXP Semiconductors ISP1582 Hi-Speed USB peripheral controller CDBGMOD[1:0] -- Interrupts for control endpoint 0 DDBGMODIN[1:0] -- Interrupts for DATA IN endpoints 1 to 7 DDBGMODOUT[1:0] -- Interrupts for DATA OUT endpoints 1 to 7 The Debug mode settings for CDBGMOD, DDBGMODIN and DDBGMODOUT allow you to individually configure when the ISP1582 sends an interrupt to the external microprocessor. Table 23 lists the available combinations. Bit INTPOL controls the signal polarity of the INT output: active HIGH or LOW, rising or falling edge. For level-triggering, bit INTLVL must be made logic 0. By setting INTLVL to logic 1, an interrupt will generate a pulse of 60 ns (edge-triggering). Table 21. Bit Symbol Reset Bus reset Access Interrupt Configuration register: bit allocation 7 1 1 R/W 6 1 1 R/W Table 22. Bit 7 to 6 5 to 4 3 to 2 1 0 5 1 1 R/W 4 1 1 R/W 3 1 1 R/W 2 1 1 R/W 1 INTLVL 0 unchanged R/W 0 INTPOL 0 unchanged R/W CDBGMOD[1:0] DDBGMODIN[1:0] DDBGMODOUT[1:0] Interrupt Configuration register: bit description Symbol CDBGMOD[1:0] DDBGMODIN[1:0] INTLVL INTPOL Description Control Endpoint 0 Debug Mode: For values, see Table 23 Data Debug Mode IN: For values, see Table 23 Interrupt Level: Selects signaling mode on output INT (0 = level; 1 = pulsed). In pulsed mode, an interrupt produces a 60 ns pulse. Interrupt Polarity: Selects signal polarity on output INT (0 = active LOW; 1 = active HIGH). DDBGMODOUT[1:0] Data Debug Mode OUT: For values, see Table 23 Table 23. Value 00h 01h 1Xh [1] Debug mode settings DDBGMODIN interrupt on all ACK and NAK interrupt on ACK interrupt on all ACK and first NAK[1] DDBGMODOUT interrupt on all ACK, NYET and NAK interrupt on ACK and NYET interrupt on all ACK, NYET and first NAK[1] CDBGMOD interrupt on all ACK and NAK interrupt on all ACK interrupt on all ACK and first NAK[1] First NAK: the first NAK on an IN or OUT token is generated after a set-up token and an ACK sequence. 8.2.4 OTG register (address: 12h) The bit allocation of the OTG register is given in Table 24. Table 24. Bit Symbol Reset Bus reset Access ISP1582_7 OTG register: bit allocation 7 reserved 6 5 DP 0 0 R/W 4 BSESSVALID R/W 3 INITCOND R/W 2 DISCV 0 0 R/W 1 VP 0 0 R/W 0 OTG 0 0 R/W (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 25 of 68 NXP Semiconductors ISP1582 Hi-Speed USB peripheral controller OTG register: bit description Table 25. Bit 7 to 6 5 Symbo Description[1][2][3] l DP reserved Data Pulsing: Used for data-line pulsing to toggle DP to generate the required data-line pulsing signal. The default value of this bit is logic 0. This bit must be cleared when data-line pulsing is completed. 4 BSESS B-Session Valid: The device can initiate another VBUS discharge sequence after VALID data-line pulsing and VBUS pulsing, and before it clears this bit and detects a session valid. This bit is latched to logic 1 once VBUS exceeds the B-device session valid threshold. Once set, it remains at logic 1. To clear this bit, write logic 1. (The ISP1582 continuously updates this bit to logic 1 when the B-session is valid. If the B-session is valid after it is cleared, it is set back to logic 1 by the ISP1582). 0 -- It implies that SRP has failed. To proceed to a normal operation, the device can restart SRP, clear bit OTG or proceed to an error handling process. 1 -- It implies that the B-session is valid. The device clears bit OTG, goes into normal operation mode, and sets bit SOFTCT (DP pull-up) in the Mode register. The OTG host has a maximum of 5 s before it responds to a session request. During this period, the ISP1582 may request to suspend. Therefore, the device firmware must wait for some time if it wishes to know the SRP result (success: if there is minimum response from the host within 5 s; failure; if there is no response from the host within 5 s). 3 INIT COND Initial Condition: Write logic 1 to clear this bit. Wait for more than 2 ms and check the bit status. If it reads logic 0, it means that VBUS remains lower than 0.8 V, and DP or DM are at SE0 during the elapsed time. The device can then start a B-device SRP. If it reads logic 1, it means that the initial condition of SRP is violated. So, the device must abort SRP. The bit is set to logic 1 by the ISP1582 when initial conditions are not met, and only writing logic 1 clears the bit. (If initial conditions are not met after this bit has been cleared, it will be set again). Remark: This implementation does not cover the case if an initial SRP condition is violated when this bit is read and data-line pulsing is started. 2 DISCV Discharge VBUS: Set to logic 1 to discharge VBUS. The device discharges VBUS before starting a new SRP. The discharge can take as long as 30 ms for VBUS to be charged less than 0.8 V. This bit must be cleared (write logic 0) before starting a session end detection. VBUS Pulsing: Used for VBUS pulsing to toggle VP to generate the required VBUS pulsing signal. This bit must be set for more than 16 ms and must be cleared before 26 ms. On-The-Go: 1 -- Enables the OTG function. The VBUS sensing functionality will be disabled. 0 -- Normal operation. All OTG control bits will be masked. Status bits are undefined. 1 VP 0 OTG [1] [2] No interrupt is designed for OTG. The VBUS interrupt, however, may assert as a side effect during the VBUS pulsing (see note 2). When OTG is in progress, the VBUS interrupt may be set because VBUS is charged over the VBUS sensing threshold or the OTG host has turned on the VBUS supply to the device. Even if the VBUS interrupt is found during SRP, the device must complete data-line pulsing and VBUS pulsing before starting the B_SESSION_VALID detection. OTG implementation applies to the device with self-power capability. If the device works in sharing mode, it must provide a switch circuit to supply power to the ISP1582 core during SRP. (c) NXP B.V. 2008. All rights reserved. [3] ISP1582_7 Product data sheet Rev. 07 -- 22 September 2008 26 of 68 NXP Semiconductors ISP1582 Hi-Speed USB peripheral controller 8.2.4.1 Session Request Protocol (SRP) The ISP1582 can initiate an SRP. The B-device initiates SRP by data-line pulsing, followed by VBUS pulsing. The A-device can detect either data-line pulsing or VBUS pulsing. The ISP1582 can initiate the B-device SRP by performing the following steps: 1. Set the OTG bit to start SRP. 2. Detect initial conditions by following the instructions given in bit INITCOND of the OTG register. 3. Start data-line pulsing: set bit DP of the OTG register to logic 1. 4. Wait for 5 ms to 10 ms. 5. Stop data-line pulsing: set bit DP of the OTG register to logic 0. 6. Start VBUS pulsing: set bit VP of the OTG register to logic 1. 7. Wait for 10 ms to 20 ms. 8. Stop VBUS pulsing: set bit VP of the OTG register to logic 0. 9. Discharge VBUS for about 30 ms: optional by using bit DISCV of the OTG register. 10. Detect bit BSESSVALID of the OTG register for a successful SRP with bit OTG cleared. 11. Once bit BSESSVALID is detected, turn on the SOFTCT bit to start normal bus enumeration. The B-device must complete both data-line pulsing and VBUS pulsing within 100 ms. Remark: When disabling OTG, data-line pulsing bit DP and VBUS pulsing bit VP must be cleared by writing logic 0. 8.2.5 Interrupt Enable register (address: 14h) This register enables or disables individual interrupt sources. The interrupt for each endpoint can individually be controlled using the associated bits IEPnRX or IEPnTX, here n represents the endpoint number. All interrupts can be globally disabled using bit GLINTENA in the Mode register (see Table 18). An interrupt is generated when the USB SIE receives or generates an ACK or NAK on the USB bus. The interrupt generation depends on Debug mode settings of bit fields CDBGMOD[1:0], DDBGMODIN[1:0] and DDBGMODOUT[1:0] in the Interrupt Configuration register. All data IN transactions use the Transmit buffers (TX), which are handled by bits DDBGMODIN[1:0]. All data OUT transactions go through the Receive buffers (RX), which are handled by bits DDBGMODOUT[1:0]. Transactions on control endpoint 0 (IN, OUT and SETUP) are handled by bits CDBGMOD[1:0]. Interrupts caused by events on the USB bus (SOF, suspend, resume, bus reset, set up and high-speed status) can also be individually controlled. A bus reset disables all enabled interrupts, except bit IEBRST (bus reset), which remains logic 1. The Interrupt Enable register consists of 4 bytes. The bit allocation is given in Table 26. ISP1582_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 27 of 68 NXP Semiconductors ISP1582 Hi-Speed USB peripheral controller Table 26. Bit Symbol Reset Bus reset Access Bit Symbol Reset Bus reset Access Bit Symbol Reset Bus reset Access Bit Symbol Reset Bus reset Access Interrupt Enable register: bit allocation 31 23 IEP6TX 0 0 R/W 15 IEP2TX 0 0 R/W 7 IEVBUS 0 0 R/W 30 22 IEP6RX 0 0 R/W 14 IEP2RX 0 0 R/W 6 IEDMA 0 0 R/W Table 27. Bit 31 to 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 IEP7TX IEP7RX IEP6TX IEP6RX IEP5TX IEP5RX IEP4TX IEP4RX IEP3TX IEP3RX IEP2TX IEP2RX IEP1TX IEP1RX IEP0TX IEP0RX IEP0SETUP 29 reserved 21 IEP5TX 0 0 R/W 13 IEP1TX 0 0 R/W 5 IEHS_STA 0 0 R/W 20 IEP5RX 0 0 R/W 12 IEP1RX 0 0 R/W 4 IERESM 0 0 R/W 19 IEP4TX 0 0 R/W 11 IEP0TX 0 0 R/W 3 IESUSP 0 0 R/W 18 IEP4RX 0 0 R/W 10 IEP0RX 0 0 R/W 2 IEPSOF 0 0 R/W 28 27 26 25 IEP7TX 0 0 R/W 17 IEP3TX 0 0 R/W 9 reserved R/W 1 IESOF 0 0 R/W 24 IEP7RX 0 0 R/W 16 IEP3RX 0 0 R/W 8 IEP0SETUP 0 0 R/W 0 IEBRST 0 1 R/W Interrupt Enable register: bit description Symbol Description reserved Logic 1 enables interrupt from the indicated endpoint. Logic 1 enables interrupt from the indicated endpoint. Logic 1 enables interrupt from the indicated endpoint. Logic 1 enables interrupt from the indicated endpoint. Logic 1 enables interrupt from the indicated endpoint. Logic 1 enables interrupt from the indicated endpoint. Logic 1 enables interrupt from the indicated endpoint. Logic 1 enables interrupt from the indicated endpoint. Logic 1 enables interrupt from the indicated endpoint. Logic 1 enables interrupt from the indicated endpoint. Logic 1 enables interrupt from the indicated endpoint. Logic 1 enables interrupt from the indicated endpoint. Logic 1 enables interrupt from the indicated endpoint. Logic 1 enables interrupt from the indicated endpoint. Logic 1 enables interrupt from the control IN endpoint 0. Logic 1 enables interrupt from the control OUT endpoint 0. reserved Logic 1 enables interrupt for the set-up data received on endpoint 0. (c) NXP B.V. 2008. All rights reserved. ISP1582_7 Product data sheet Rev. 07 -- 22 September 2008 28 of 68 NXP Semiconductors ISP1582 Hi-Speed USB peripheral controller Interrupt Enable register: bit description ...continued Symbol IEVBUS IEDMA IEHS_STA IERESM IESUSP IEPSOF IESOF IEBRST Description Logic 1 enables interrupt for VBUS sensing. Logic 1 enables interrupt on the DMA Interrupt Reason register change detection. Logic 1 enables interrupt on detection of a high-speed status change. Logic 1 enables interrupt on detection of a resume state. Logic 1 enables interrupt on detection of a suspend state. Logic 1 enables interrupt on detection of a pseudo SOF. Logic 1 enables interrupt on detection of an SOF. Logic 1 enables interrupt on detection of a bus reset. Table 27. Bit 7 6 5 4 3 2 1 0 8.3 Data flow registers 8.3.1 Endpoint Index register (address: 2Ch) The Endpoint Index register selects a target endpoint for register access by the microcontroller. The register consists of 1 byte, and the bit allocation is shown in Table 28. The following registers are indexed: * * * * * * Buffer length Buffer status Control function Data port Endpoint MaxPacketSize Endpoint type For example, to access the OUT data buffer of endpoint 1 using the Data Port register, the Endpoint Index register must be written first with 02h. Remark: The Endpoint Index register and the DMA Endpoint register must not point to the same endpoint, irrespective of IN and OUT. Remark: The delay time from the Write Endpoint Index register to the Read Data Port register must be at least 190 ns. Remark: The delay time from the Write Endpoint Index register to the Write Data Port register must be at least 100 ns. Table 28. Bit Symbol Reset Bus reset Access R/W Endpoint Index register: bit allocation 7 reserved R/W 6 5 EP0SETUP 1 unchanged R/W 0 0 R/W 4 3 0 0 R/W 2 0 0 R/W 1 0 0 R/W 0 DIR 0 0 R/W ENDPIDX[3:0] ISP1582_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 29 of 68 NXP Semiconductors ISP1582 Hi-Speed USB peripheral controller Endpoint Index register: bit description Symbol EP0SETUP Description reserved Endpoint 0 Setup: Selects the SETUP buffer of endpoint 0. 0 -- Data buffer 1 -- SETUP buffer Must be logic 0 for access to endpoints other than set-up token buffer. Table 29. Bit 7 to 6 5 4 to 1 ENDPIDX[3:0] Endpoint Index: Selects the target endpoint for register access of buffer length, buffer status, control function, data port, endpoint type and MaxPacketSize. Direction: Sets the target endpoint as IN or OUT. 0 -- Target endpoint refers to OUT (RX) FIFO 1 -- Target endpoint refers to IN (TX) FIFO 0 DIR Table 30. SETUP Addressing of endpoint buffers EP0SETUP 1 0 0 0 0 ENDPIDX 00h 00h 00h 0Xh 0Xh DIR 0 0 1 0 1 Buffer name Control OUT Control IN Data OUT Data IN 8.3.2 Control Function register (address: 28h) The Control Function register performs the buffer management on endpoints. It consists of 1 byte, and the bit configuration is given in Table 31. Register bits can stall, clear or validate any enabled data endpoint. Before accessing this register, the Endpoint Index register must first be written to specify the target endpoint. Table 31. Bit Symbol Reset Bus reset Access Control Function register: bit allocation 7 6 reserved 5 4 CLBUF 0 0 R/W 3 VENDP 0 0 R/W 2 DSEN 0 0 W 1 STATUS 0 0 R/W 0 STALL 0 0 R/W ISP1582_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 30 of 68 NXP Semiconductors ISP1582 Hi-Speed USB peripheral controller Control Function register: bit description Symbol CLBUF Description reserved Clear Buffer: Logic 1 clears the TX or RX buffer of the indexed endpoint. The RX buffer is automatically cleared once the endpoint is completely read. This bit is set only when it is necessary to forcefully clear the buffer. Remark: If using double buffer, to clear both the buffers issue the CLBUF command two times. For details on clearing buffers, refer to Ref. 4 "ISP1582/83 and ISP1761 clearing an IN buffer (AN10045)". Table 32. Bit 7 to 5 4 3 VENDP Validate Endpoint: Logic 1 validates data in the TX FIFO of an IN endpoint to send on the next IN token. In general, the endpoint is automatically validated when its FIFO byte count has reached endpoint MaxPacketSize. This bit is set only when it is necessary to validate the endpoint with the FIFO byte count, which is below endpoint MaxPacketSize. Remark: Use either bit VENDP or register Buffer Length to validate endpoint FIFO with FIFO bytes. 2 DSEN Data Stage Enable: This bit controls the response of the ISP1582 to a control transfer. After the completion of the set-up stage, firmware must determine whether a data stage is required. For control OUT, firmware will set this bit and the ISP1582 goes into the data stage. Otherwise, the ISP1582 will NAK the data stage transfer. For control IN, firmware will set this bit before writing data to the TX FIFO and validate the endpoint. If no data stage is required, firmware can immediately set the STATUS bit after the set-up stage. Remark: The DSEN bit is cleared once the OUT token is acknowledged by the device and the IN token is acknowledged by the PC host. This bit cannot be read back and reading this bit will return logic 0. 1 STATUS Status Acknowledge: Only applicable for control IN or OUT. This bit controls the generation of ACK or NAK during the status stage of a SETUP transfer. It is automatically cleared when the status stage is completed, or when a SETUP token is received. No interrupt signal will be generated. 0 -- Sends NAK 1 -- Sends an empty packet following the IN token (peripheral-to-host) or ACK following the OUT token (host-to-peripheral). Remark: The STATUS bit is cleared to zero once the zero-length packet is acknowledged by the device or the PC host. Remark: Data transfers preceding the status stage must first be fully completed before the STATUS bit can be set. 0 STALL Stall Endpoint: Logic 1 stalls the indexed endpoint. This bit is not applicable for isochronous transfers. Remark: Stalling a data endpoint will confuse the Data Toggle bit about the stalled endpoint because the internal logic picks up from where it is stalled. Therefore, the Data Toggle bit must be reset by disabling and re-enabling the corresponding endpoint (by setting bit ENABLE to logic 0, followed by logic 1 in the Endpoint Type register) to reset the PID. 8.3.3 Data Port register (address: 20h) This 2-byte register provides direct access for a microcontroller to the FIFO of the indexed endpoint. The bit allocation is shown in Table 33. ISP1582_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 31 of 68 NXP Semiconductors ISP1582 Hi-Speed USB peripheral controller Peripheral-to-host (IN endpoint): After each write action, an internal counter is auto incremented by two to the next location in the TX FIFO. When all bytes are written (FIFO byte count = endpoint MaxPacketSize), the buffer is automatically validated. The data packet will then be sent on the next IN token. When it is necessary to validate the endpoint whose byte count is less than MaxPacketSize, it can be done using the Control Function register (bit VENDP) or the Buffer Length register. Remark: The buffer can automatically be validated by using the Buffer Length register (see Table 35). Host-to-peripheral (OUT endpoint): After each read action, an internal counter is auto decremented by two to the next location in the RX FIFO. When all bytes are read, buffer contents are automatically cleared. A new data packet can then be received on the next OUT token. Buffer contents can also be cleared using the Control Function register (bit CLBUF), when it is necessary to forcefully clear contents. Remark: The delay time from the Write Endpoint Index register to the Read Data Port register must be at least 190 ns. Remark: The delay time from the Write Endpoint Index register to the Write Data Port register must be at least 100 ns. Table 33. Bit Symbol Reset Bus reset Access Bit Symbol Reset Bus reset Access 0 0 R/W 0 0 R/W Table 34. Bit 7 to 0 0 0 R/W 0 0 R/W 7 0 0 R/W 6 0 0 R/W 5 Data Port register: bit allocation 15 14 13 12 0 0 R/W 4 0 0 R/W 11 0 0 R/W 3 0 0 R/W 10 0 0 R/W 2 0 0 R/W 9 0 0 R/W 1 0 0 R/W 8 0 0 R/W 0 0 0 R/W DATAPORT[15:8] DATAPORT[7:0] Data Port register: bit description Symbol DATAPORT[7:0] Description data (lower byte) 15 to 8 DATAPORT[15:8] data (upper byte) 8.3.4 Buffer Length register (address: 1Ch) This register determines the current packet size (DATACOUNT) of the indexed endpoint FIFO. The bit allocation is given in Table 35. The Buffer Length register is automatically loaded with the FIFO size, when the Endpoint MaxPacketSize register is written (see Table 39). A smaller value can be written when required. After a bus reset, the Buffer Length register is made zero. ISP1582_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 32 of 68 NXP Semiconductors ISP1582 Hi-Speed USB peripheral controller IN endpoint: When data transfer is performed in multiples of MaxPacketSize, the Buffer Length register is not significant. This register is useful only when transferring data that is not a multiple of MaxPacketSize. The following two examples demonstrate the significance of the Buffer Length register. Example 1: Consider that the transfer size is 512 bytes and the MaxPacketSize is programmed as 64 bytes, the Buffer Length register need not be filled. This is because the transfer size is a multiple of MaxPacketSize, and MaxPacketSize packets will be automatically validated because the last packet is also of MaxPacketSize. Example 2: Consider that the transfer size is 510 bytes and the MaxPacketSize is programmed as 64 bytes, the Buffer Length register must be filled with 62 bytes just before the microprocessor writes the last packet of 62 bytes. This ensures that the last packet, which is a short packet of 62 bytes, is automatically validated. Use bit VENDP in the Control register if you are not using the Buffer Length register. This is applicable only to the PIO mode access. OUT endpoint: The DATACOUNT value is automatically initialized to the number of data bytes sent by the host on each ACK. Remark: When using a 16-bit microprocessor bus, the last byte of an odd-sized packet is output as the lower byte (LSByte). Remark: Buffer Length is valid only after an interrupt is generated for the OUT endpoint. Table 35. Bit Symbol Reset Bus reset Access Bit Symbol Reset Bus reset Access 0 0 R/W 0 0 R/W Table 36. Bit 15 to 0 0 0 R/W 0 0 R/W 7 0 0 R/W 6 0 0 R/W 5 Buffer Length register: bit allocation 15 14 13 12 0 0 R/W 4 0 0 R/W 11 0 0 R/W 3 0 0 R/W 10 0 0 R/W 2 0 0 R/W 9 0 0 R/W 1 0 0 R/W 8 0 0 R/W 0 0 0 R/W DATACOUNT[15:8] DATACOUNT[7:0] Buffer Length register: bit description Symbol DATACOUNT[15:0] Description Data Count: Determines the current packet size of the indexed endpoint FIFO. 8.3.5 Buffer Status register (address: 1Eh) This register is accessed using index. The endpoint index must first be set before accessing this register for the corresponding endpoint. It reflects the status of the double buffered endpoint FIFO. Remark: This register is not applicable to the control endpoint. ISP1582_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 33 of 68 NXP Semiconductors ISP1582 Hi-Speed USB peripheral controller Remark: For endpoint IN data transfer, firmware must ensure a 200 ns delay between writing of the data packet and reading the Buffer Status register. For endpoint OUT data transfer, firmware must also ensure a 200 ns delay between receiving the endpoint interrupt and reading the Buffer Status register. For more information, refer to Ref. 3 "Using ISP1582/3 in a composite device application with alternate settings (AN10071)". Table 37 shows the bit allocation of the Buffer Status register. Table 37. Bit Symbol Reset Bus reset Access Table 38. Bit 7 to 2 1 to 0 BUF[1:0] Buffer Status register: bit allocation 7 6 5 reserved 4 3 2 1 BUF1 0 0 R 0 BUF0 0 0 R Buffer Status register: bit description Symbol Description reserved Buffer: 00 -- The buffers are not filled. 01 -- One of the buffers is filled. 10 -- One of the buffers is filled. 11 -- Both the buffers are filled. 8.3.6 Endpoint MaxPacketSize register (address: 04h) This register determines the maximum packet size for all endpoints, except set-up token buffer, control IN and control OUT. The register contains 2 bytes, and the bit allocation is given in Table 39. Each time the register is written, the Buffer Length register of the corresponding endpoint is re-initialized to the FFOSZ field value. Bits NTRANS control the number of transactions allowed in a single microframe (for high-speed isochronous and interrupt endpoints only). Table 39. Bit Symbol Reset Bus reset Access Bit Symbol Reset Bus reset Access 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W 7 Endpoint MaxPacketSize register: bit allocation 15 14 reserved 6 5 13 12 0 0 R/W 4 FFOSZ[7:0] 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W 11 0 0 R/W 3 10 0 0 R/W 2 9 FFOSZ[10:8] 0 0 R/W 1 0 0 R/W 0 8 NTRANS[1:0] ISP1582_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 34 of 68 NXP Semiconductors ISP1582 Hi-Speed USB peripheral controller Endpoint MaxPacketSize register: bit description Symbol NTRANS[1:0] Description reserved Number of Transactions: HS mode only. 00 -- 1 packet per microframe 01 -- 2 packets per microframe 10 -- 3 packets per microframe 11 -- reserved These bits are applicable only for isochronous or interrupt transactions. Table 40. Bit 15 to 13 12 to 11 10 to 0 FFOSZ[10:0] FIFO Size: Sets the FIFO size, in bytes, for the indexed endpoint. Applies to both high-speed and full-speed operations. The ISP1582 supports all the transfers given in Ref. 1 "Universal Serial Bus Specification Rev. 2.0". Each programmable FIFO can independently be configured using its Endpoint MaxPacketSize register (R/W: 04h), but the total physical size of all enabled endpoints (IN plus OUT) including set-up token buffer, control IN and control OUT, must not exceed 8192 bytes. 8.3.7 Endpoint Type register (address: 08h) This register sets the endpoint type of the indexed endpoint: isochronous, bulk or interrupt. It also serves to enable the endpoint and configure it for double buffering. Automatic generation of an empty packet for a zero-length TX buffer can be disabled using bit NOEMPKT. The register contains 2 bytes, and the bit allocation is shown in Table 41. Table 41. Bit Symbol Reset Bus reset Access Bit Symbol Reset Bus reset Access 7 6 reserved 5 4 NOEMPKT 0 0 R/W Endpoint Type register: bit allocation 15 14 13 12 reserved 3 ENABLE 0 0 R/W 2 DBLBUF 0 0 R/W 1 0 0 R/W 0 0 0 R/W ENDPTYP[1:0] 11 10 9 8 ISP1582_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 35 of 68 NXP Semiconductors ISP1582 Hi-Speed USB peripheral controller Endpoint Type register: bit description Symbol NOEMPKT Description reserved No Empty Packet: Logic 0 causes the ISP1582 to return a null length packet for the IN token after the DMA IN transfer is complete. For the IN DMA transfer, which does not require a null length packet after DMA completion, set to logic 1 to disable the generation of the null length packet. Endpoint Enable: Logic 1 enables the FIFO of the indexed endpoint. The memory size is allocated as specified in the Endpoint MaxPacketSize register. Logic 0 disables the FIFO. Remark: Stalling a data endpoint will confuse the Data Toggle bit on the stalled endpoint because the internal logic picks up from where it has stalled. Therefore, the Data Toggle bit must be reset by disabling and re-enabling the corresponding endpoint (by setting bit ENABLE to logic 0 or logic 1 in the Endpoint Type register) to reset the PID. Table 42. Bit 15 to 5 4 3 ENABLE 2 DBLBUF Double Buffering: Logic 1 enables double buffering for the indexed endpoint. Logic 0 disables double buffering. Remark: When performing a write to two empty buffers, ensure that a minimum of 200 ns delay is provided from the last write of the first buffer to the first write of the second buffer. Otherwise, the first few data bytes may not be written to the second buffer, causing data corruption. 1 to 0 ENDPTYP[1:0] Endpoint Type: These bits select the endpoint type as follows. 00 -- Not used 01 -- Isochronous 10 -- Bulk 11 -- Interrupt 8.4 DMA registers The Generic DMA (GDMA) transfer can be done by writing the proper opcode in the DMA Command register. Control bits are given in Table 43. GDMA read/write (opcode = 00h/01h) for GDMA mode: Depending on the MODE[1:0] bits set in the DMA configuration register, the DACK, DIOR or DIOW signal strobes data. These signals are driven by the external DMA controller. GDMA mode can operate in either counter mode or EOT-only mode. In counter mode, bit DIS_XFER_CNT in the DMA Configuration register must be set to logic 0. The DMA Transfer Counter register must be programmed before any DMA command is issued. The DMA transfer counter is set by writing from the LSByte to the MSByte (address: 34h to 37h). The DMA transfer count is internally updated only after the MSByte is written. Once the DMA transfer is started, the transfer counter starts decrementing and on reaching 0, bit DMA_XFER_OK is set and an interrupt is generated by the ISP1582. If the DMA master wishes to terminate the DMA transfer, it can issue an EOT signal to the ISP1582. This EOT signal overrides the transfer counter and can terminate the DMA transfer at any time. ISP1582_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 36 of 68 NXP Semiconductors ISP1582 Hi-Speed USB peripheral controller In EOT-only mode, DIS_XFER_CNT must be set to logic 1. Although the DMA transfer counter can still be programmed, it will not have any effect on the DMA transfer. The DMA transfer will start once the DMA command is issued. Any of the following three ways will terminate this DMA transfer: * Detecting an external EOT * Detecting an internal EOT (short packet on an OUT token) * Issuing a GDMA stop command There are three interrupts programmable to differentiate the method of DMA termination: bits INT_EOT, EXT_EOT and DMA_XFER_OK in the DMA Interrupt Reason register. For details, see Table 55. Table 43. Control bits for GDMA read/write (opcode = 00h/01h) Description determines the active read/write data strobe signals selects the DMA bus width: 8 or 16 bits disables the use of the DMA Transfer Counter selects the polarity of the EOT signal determines whether the data is to be byte swapped or normal; applicable only in 16-bit mode select polarity of DMA handshake signals Table 51 Reference Table 49 Control bits MODE[1:0] WIDTH DIS_XFER_CNT DMA Hardware register EOT_POL ENDIAN[1:0] ACK_POL, DREQ_POL, WRITE_POL, READ_POL DMA Configuration register Remark: The DMA bus defaults to 3-state, until a DMA command is executed. All the other control signals are not 3-stated. 8.4.1 DMA Command register (address: 30h) The DMA Command register is a 1-byte register (for bit allocation, see Table 44) that initiates all DMA transfer activity on the DMA controller. The register is write-only: reading it will return FFh. Remark: The DMA bus will be in 3-state, until a DMA command is executed. Table 44. Bit Symbol Reset Bus reset Access 1 1 W Table 45. Bit 7 to 0 1 1 W 1 1 W DMA Command register: bit allocation 7 6 5 4 1 1 W 3 1 1 W 2 1 1 W 1 1 1 W 0 1 1 W DMA_CMD[7:0] DMA Command register: bit description Symbol DMA_CMD[7:0] Description DMA command code; see Table 46. ISP1582_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 37 of 68 NXP Semiconductors ISP1582 Hi-Speed USB peripheral controller Table 46. Code 00h 01h DMA commands Name GDMA Read GDMA Write Description Generic DMA IN token transfer: Data is transferred from the external DMA bus to the internal buffer. Strobe: DIOW by the external DMA controller. Generic DMA OUT token transfer: Data is transferred from the internal buffer to the external DMA bus. Strobe: DIOR by the external DMA controller. reserved 02h to 0Dh 0Eh 0Fh Validate Buffer Validate Buffer (for debugging only): Request from the microcontroller to validate the endpoint buffer, following a DMA-to-USB data transfer. Clear Buffer Clear Buffer: Request from the microcontroller to clear the endpoint buffer, after a DMA-to-USB data transfer. Logic 1 clears the TX buffer of the indexed endpoint; the RX buffer is not affected. The TX buffer is automatically cleared once data is sent on the USB bus. This bit is set only when it is necessary to forcefully clear the buffer. Remark: If using double buffer, to clear both the buffers issue the Clear Buffer command two times, that is, set and clear this bit two times. 10h 11h Reset DMA reserved Reset DMA: Initializes the DMA core to its power-on reset state. Remark: When the DMA core is reset during the Reset DMA command, the DREQ, DACK, DIOW and DIOR handshake pins will temporarily be asserted. This can confuse the external DMA controller. To prevent this, start the external DMA controller only after the DMA reset. 12h 13h GDMA Stop reserved GDMA stop: This command stops the GDMA data transfer. Any data in the OUT endpoint that is not transferred by the DMA will remain in the buffer. The FIFO data for the IN endpoint will be written to the endpoint buffer. An interrupt bit will be set to indicate the completion of the DMA Stop command. Remark: For the DMA OUT transfer, if the DMA Burst Counter register is programmed to some value, for example 512 bytes, and if a GDMA Stop command is issued in the middle of a transfer, the transfer will continue until the end of the burst size (512 bytes). Issuing a GDMA stop command does not allow the ISP1582 to stop in the middle of the burst. It can only be stopped in between bursts. 14h to FFh - reserved 8.4.2 DMA Transfer Counter register (address: 34h) This 4-byte register sets up the total byte count for a DMA transfer (DMACR). It indicates the remaining number of bytes left for transfer. The bit allocation is given in Table 47. For IN endpoint -- Because there is a FIFO in the ISP1582 DMA controller, some data may remain in the FIFO during the DMA transfer. The maximum FIFO size is 8 bytes, and the maximum delay time for data to be shifted to endpoint buffer is 60 ns. For OUT endpoint -- Data will not be cleared from the endpoint buffer, until all the data is read from the DMA FIFO. If the DMA counter is disabled in the DMA transfer, it will still decrement and rollover when it reaches zero. Table 47. Bit Symbol DMA Transfer Counter register: bit allocation 31 30 29 28 27 26 25 24 DMACR4 = DMACR[31:24] ISP1582_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 38 of 68 NXP Semiconductors ISP1582 Hi-Speed USB peripheral controller Table 47. Bit Reset Bus reset Access Bit Symbol Reset Bus reset Access Bit Symbol Reset Bus reset Access Bit Symbol Reset Bus reset Access DMA Transfer Counter register: bit allocation ...continued 31 0 0 R/W 23 0 0 R/W 15 0 0 R/W 7 0 0 R/W 30 0 0 R/W 22 0 0 R/W 14 0 0 R/W 6 0 0 R/W Table 48. Bit 31 to 24 23 to 16 15 to 8 7 to 0 29 0 0 R/W 21 0 0 R/W 13 0 0 R/W 5 0 0 R/W 28 0 0 R/W 20 0 0 R/W 12 0 0 R/W 4 0 0 R/W 27 0 0 R/W 19 0 0 R/W 11 0 0 R/W 3 0 0 R/W 26 0 0 R/W 18 0 0 R/W 10 0 0 R/W 2 0 0 R/W 25 0 0 R/W 17 0 0 R/W 9 0 0 R/W 1 0 0 R/W 24 0 0 R/W 16 0 0 R/W 8 0 0 R/W 0 0 0 R/W DMACR3 = DMACR[23:16] DMACR2 = DMACR[15:8] DMACR1 = DMACR[7:0] DMA Transfer Counter register: bit description Symbol DMACR4 = DMACR[31:24] DMACR3 = DMACR[23:16] DMACR2 = DMACR[15:8] DMACR1 = DMACR[7:0] Description DMA transfer counter byte 4 (MSByte) DMA transfer counter byte 3 DMA transfer counter byte 2 DMA transfer counter byte 1 (LSByte) 8.4.3 DMA Configuration register (address: 38h) This register defines the DMA configuration for GDMA mode. The DMA Configuration register consists of 2 bytes. The bit allocation is given in Table 49. Table 49. Bit Symbol Reset Bus reset Access Bit Symbol Reset Bus reset Access ISP1582_7 DMA Configuration register: bit allocation 15 7 DIS_ XFER_CNT 0 0 R/W 14 6 13 5 reserved 0 0 R/W 12 reserved 4 3 MODE[1:0] 0 0 R/W 2 1 reserved 0 WIDTH 1 1 R/W 11 10 9 8 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 39 of 68 NXP Semiconductors ISP1582 Hi-Speed USB peripheral controller DMA Configuration register: bit description Symbol Description[1] reserved Table 50. Bit 15 to 8 7 6 to 4 3 to 2 DIS_XFER_CNT Disable Transfer Count: Logic 1 disables the DMA Transfer Counter (see Table 47). MODE[1:0] reserved Mode: These bits affect GDMA handshake signals. 00 -- DIOW strobes data from the DMA bus into the ISP1582; DIOR puts data from the ISP1582 on the DMA bus. 01 -- DACK strobes data from the DMA bus into the ISP1582; DIOR puts data from the ISP1582 on the DMA bus. 10 -- DACK strobes data from the DMA bus into the ISP1582 and also puts data from the ISP1582 on the DMA bus. 11 -- reserved 1 0 WIDTH reserved Width: This bit selects the DMA bus width. 0 -- 8-bit data bus 1 -- 16-bit data bus [1] The DREQ pin will be driven only after performing a write access to the DMA Configuration register (that is, after configuring the DMA Configuration register). 8.4.4 DMA Hardware register (address: 3Ch) The DMA Hardware register consists of 1 byte. The bit allocation is shown in Table 51. This register determines the polarity of bus control signals (EOT, DACK, DREQ, DIOR and DIOW). It also controls whether the upper and lower parts of the data bus are swapped (bits ENDIAN[1:0]). Table 51. Bit Symbol Reset Bus reset Access DMA Hardware register: bit allocation 7 6 5 EOT_POL 0 0 R/W 4 reserved 3 ACK_POL 0 0 R/W 2 DREQ_ POL 1 1 R/W 1 WRITE_ POL 0 0 R/W 0 READ_ POL 0 0 R/W ENDIAN[1:0] 0 0 R/W 0 0 R/W ISP1582_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 40 of 68 NXP Semiconductors ISP1582 Hi-Speed USB peripheral controller DMA Hardware register: bit description Description Endian: These bits determine whether the data bus is swapped between the internal RAM and the DMA bus. 00 -- Normal data representation; 16-bit bus: MSByte on DATA[15:8], LSByte on DATA[7:0] 01 -- Swapped data representation; 16-bit bus: MSByte on DATA[7:0], LSByte on DATA[15:8] 10 -- reserved 11 -- reserved Remark: While operating with the 8-bit data bus, bits ENDIAN[1:0] must always be set to 00b. Table 52. Bit 7 to 6 Symbol ENDIAN[1:0] 5 EOT_POL EOT Polarity: Selects the polarity of the End-Of-Transfer input. 0 -- EOT is active LOW 1 -- EOT is active HIGH 4 3 ACK_POL reserved; must be set to logic 0. Acknowledgment Polarity: Selects the DMA acknowledgment polarity. 0 -- DACK is active LOW 1 -- DACK is active HIGH 2 DREQ_POL DREQ Polarity: Selects the DMA request polarity. 0 -- DREQ is active LOW 1 -- DREQ is active HIGH 1 WRITE_POL Write Polarity: Selects the DIOW strobe polarity. 0 -- DIOW is active LOW 1 -- DIOW is active HIGH 0 READ_POL Read Polarity: Selects the DIOR strobe polarity. 0 -- DIOR is active LOW 1 -- DIOR is active HIGH 8.4.5 DMA Interrupt Reason register (address: 50h) This 2-byte register shows the source(s) of DMA interrupt. Each bit is refreshed after a DMA command is executed. An interrupt source is cleared by writing logic 1 to the corresponding bit. On detecting the interrupt, the external microprocessor must read the DMA Interrupt Reason register and mask it with the corresponding bits in the DMA Interrupt Enable register to determine the source of the interrupt. The bit allocation is given in Table 53. Table 53. Bit Symbol Reset Bus reset Access DMA Interrupt Reason register: bit allocation 15 TEST3 R 14 reserved 13 12 GDMA_ STOP 0 0 R/W 11 EXT_EOT 0 0 R/W 10 INT_EOT 0 0 R/W 9 reserved R/W 8 DMA_ XFER_OK 0 0 R/W ISP1582_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 41 of 68 NXP Semiconductors ISP1582 Hi-Speed USB peripheral controller 6 5 4 reserved 3 2 1 0 - Bit Symbol Reset Bus reset Access 7 - Table 54. Bit 15 DMA Interrupt Reason register: bit description Symbol TEST3 Description This bit is set when the DMA transfer for a packet (OUT transfer) terminates before the whole packet has been transferred. This bit is a status bit, and the corresponding mask bit of this register is always logic 0. Writing any value other than logic 0 has no effect. reserved GDMA Stop: When the GDMA_STOP command is issued to DMA Command registers, it means the DMA transfer has successfully terminated. External EOT: Logic 1 indicates that an external EOT is detected. Internal EOT: Logic 1 indicates that an internal EOT is detected; see Table 55. reserved 14 to 13 12 GDMA_STOP 11 10 9 8 7 to 0 Table 55. INT_EOT 1 1 0 EXT_EOT INT_EOT - DMA_XFER_OK DMA Transfer OK: Logic 1 indicates that the DMA transfer is completed (DMA Transfer Counter has become zero). reserved Internal EOT-functional relation with bit DMA_XFER_OK DMA_XFER_OK 0 1 1 Description During the DMA transfer, there is a premature termination with short packet. DMA transfer is completed with short packet and the DMA transfer counter has reached 0. DMA transfer is completed without any short packet and the DMA transfer counter has reached 0. 8.4.6 DMA Interrupt Enable register (address: 54h) This 2-byte register controls the interrupt generation of the source bits in the DMA Interrupt Reason register. The bit allocation is given in Table 56. The bit description is given in Table 54. Logic 1 enables the interrupt generation. After a bus reset, interrupt generation is disabled, with the values turning to logic 0. Table 56. Bit Symbol Reset Bus reset Access ISP1582_7 DMA Interrupt Enable register: bit allocation 15 TEST4 R 14 reserved 13 12 IE_GDMA_ STOP 0 0 R/W 11 IE_EXT_ EOT 0 0 R/W 10 IE_INT_ EOT 0 0 R/W 9 reserved 0 0 R/W 8 IE_DMA_ XFER_OK 0 0 R/W (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 42 of 68 NXP Semiconductors ISP1582 Hi-Speed USB peripheral controller 6 0 0 R/W 5 0 0 R/W 4 reserved 0 0 R/W 3 0 0 R/W 2 0 0 R/W 1 0 0 R/W 0 0 0 R/W Bit Symbol Reset Bus reset Access 7 0 0 R/W 8.4.7 DMA Endpoint register (address: 58h) This 1-byte register selects a USB endpoint FIFO as a source or destination for DMA transfers. The bit allocation is given in Table 57. Table 57. Bit Symbol Reset Bus reset Access Table 58. Bit 7 to 4 3 to 1 0 DMA Endpoint register: bit allocation 7 6 reserved 0 0 R/W 5 4 3 2 EPIDX[2:0] 0 0 R/W 0 0 R/W 1 0 DMADIR 0 0 R/W DMA Endpoint register: bit description Symbol EPIDX[2:0] DMADIR Description reserved Endpoint Index: Selects the indicated endpoint for DMA access DMA Direction: 0 -- Selects the RX/OUT FIFO for DMA read transfers 1 -- Selects the TX/IN FIFO for DMA write transfers The DMA Endpoint register must not reference the endpoint that is indexed by the Endpoint Index register (2Ch) at any time. Doing so will result in data corruption. Therefore, if the DMA Endpoint register is unused, point it to an unused endpoint. If the DMA Endpoint register, however, is pointed to an active endpoint, the firmware must not reference the same endpoint on the Endpoint Index register. 8.4.8 DMA Burst Counter register (address: 64h) Table 59 shows the bit allocation of the 2-byte register. Table 59. Bit Symbol Reset Bus reset Access Bit Symbol Reset Bus reset Access 0 0 R/W 0 0 R/W 0 0 R/W 7 DMA Burst Counter register: bit allocation 15 14 reserved 6 5 0 0 R/W 4 0 0 R/W 0 0 R/W 3 0 0 R/W 13 12 11 10 BURSTCOUNTER[12:8] 0 0 R/W 2 0 0 R/W 0 0 R/W 1 1 1 R/W 0 0 R/W 0 0 0 R/W 9 8 BURSTCOUNTER[7:0] ISP1582_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 43 of 68 NXP Semiconductors ISP1582 Hi-Speed USB peripheral controller DMA Burst Counter register: bit description Symbol BURST COUNTER [12:0] Description reserved Burst Counter: This register defines the burst length. The counter must be programmed to be a multiple of two in 16-bit mode. The value of the burst counter must be programmed so that the burst counter is a factor of the buffer size. It is used to determine the assertion and deassertion of DREQ. Table 60. Bit 15 to 13 12 to 0 8.5 General registers 8.5.1 Interrupt register (address: 18h) The Interrupt register consists of 4 bytes. The bit allocation is given in Table 61. When a bit is set in the Interrupt register, it indicates that the hardware condition for an interrupt has occurred. When the Interrupt register content is nonzero, the INT output will be asserted corresponding to the Interrupt Enable register. On detecting the interrupt, the external microprocessor must read the Interrupt register and mask it with the corresponding bits in the Interrupt Enable register to determine the source of the interrupt. Each endpoint buffer has a dedicated interrupt bit (EPnTX, EPnRX). In addition, various bus states can generate an interrupt: resume, suspend, pseudo SOF, SOF and bus reset. The DMA controller only has one interrupt bit: the source for a DMA interrupt is shown in the DMA Interrupt Reason register. Each interrupt bit can individually be cleared by writing logic 1. The DMA Interrupt bit can be cleared by writing logic 1 to the related interrupt source bit in the DMA Interrupt Reason register, followed by writing logic 1 to the DMA bit of the Interrupt register. Table 61. Bit Symbol Reset Bus reset Access Bit Symbol Reset Bus reset Access Bit Symbol Reset Bus reset Access 23 EP6TX 0 0 R/W 15 EP2TX 0 0 R/W 22 EP6RX 0 0 R/W 14 EP2RX 0 0 R/W 21 EP5TX 0 0 R/W 13 EP1TX 0 0 R/W Interrupt register: bit allocation 31 30 29 reserved 20 EP5RX 0 0 R/W 12 EP1RX 0 0 R/W 19 EP4TX 0 0 R/W 11 EP0TX 0 0 R/W 18 EP4RX 0 0 R/W 10 EP0RX 0 0 R/W 28 27 26 25 EP7TX 0 0 R/W 17 EP3TX 0 0 R/W 9 reserved 24 EP7RX 0 0 R/W 16 EP3RX 0 0 R/W 8 EP0SETUP 0 0 R/W ISP1582_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 44 of 68 NXP Semiconductors ISP1582 Hi-Speed USB peripheral controller 6 DMA 0 0 R/W 5 HS_STAT 0 0 R/W 4 RESUME 0 0 R/W 3 SUSP 0 0 R/W 2 PSOF 0 0 R/W 1 SOF 0 0 R/W 0 BRESET 0 1 R/W Bit Symbol Reset Bus reset Access 7 VBUS 0 0 R/W Table 62. Bit 31 to 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 Interrupt register: bit description Symbol EP7TX EP7RX EP6TX EP6RX EP5TX EP5RX EP4TX EP4RX EP3TX EP3RX EP2TX EP2RX EP1TX EP1RX EP0TX EP0RX EP0SETUP VBUS DMA HS_STAT Description reserved logic 1 indicates the endpoint 7 TX buffer as interrupt source logic 1 indicates the endpoint 7 RX buffer as interrupt source logic 1 indicates the endpoint 6 TX buffer as interrupt source logic 1 indicates the endpoint 6 RX buffer as interrupt source logic 1 indicates the endpoint 5 TX buffer as interrupt source logic 1 indicates the endpoint 5 RX buffer as interrupt source logic 1 indicates the endpoint 4 TX buffer as interrupt source logic 1 indicates the endpoint 4 RX buffer as interrupt source logic 1 indicates the endpoint 3 TX buffer as interrupt source logic 1 indicates the endpoint 3 RX buffer as interrupt source. logic 1 indicates the endpoint 2 TX buffer as interrupt source logic 1 indicates the endpoint 2 RX buffer as interrupt source logic 1 indicates the endpoint 1 TX buffer as interrupt source logic 1 indicates the endpoint 1 RX buffer as interrupt source logic 1 indicates the endpoint 0 data TX buffer as interrupt source logic 1 indicates the endpoint 0 data RX buffer as interrupt source reserved logic 1 indicates that a SETUP token was received on endpoint 0 logic 1 indicates a transition from LOW to HIGH transition on VBUS DMA Status: Logic 1 indicates a change in the DMA Interrupt Reason register. High-Speed Status: Logic 1 indicates a change from full-speed to high-speed mode (HS connection). This bit is not set when the system goes into full-speed suspend. Resume Status: Logic 1 indicates that a status change from suspend to resume (active) was detected. Suspend Status: Logic 1 indicates that a status change from active to suspend was detected on the bus. Pseudo SOF Interrupt: Logic 1 indicates that a pseudo SOF or SOF was received. Pseudo SOF is an internally generated clock signal (full-speed: 1 ms period, high-speed: 125 s period) that is not synchronized to the USB bus SOF or SOF. SOF Interrupt: Logic 1 indicates that a SOF or SOF was received. Bus Reset: Logic 1 indicates that a USB bus reset was detected. When bit OTG in the OTG register is set, BRESET will not be set; instead, this interrupt bit will report SE0 on DP and DM for 2 ms. 4 3 2 RESUME SUSP PSOF 1 0 SOF BRESET ISP1582_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 45 of 68 NXP Semiconductors ISP1582 Hi-Speed USB peripheral controller 8.5.2 Chip ID register (address: 70h) This read-only register contains the chip identification and hardware version numbers. Firmware must check this information to determine functions and features supported. The register contains 3 bytes, and the bit allocation is shown in Table 63. Table 63. Bit Symbol Reset Bus reset Access Bit Symbol Reset Bus reset Access Bit Symbol Reset Bus reset Access 0 0 R 0 0 R Table 64. Bit 23 to 16 15 to 8 7 to 0 1 1 R 1 1 R 7 0 0 R 6 0 0 R 5 0 0 R 4 1 1 R 0 0 R 15 0 0 R 14 0 0 R 13 Chip ID register: bit allocation 23 22 21 20 1 1 R 12 CHIPID[7:0] 0 0 R 3 0 0 R 0 0 R 2 0 0 R 1 1 R 1 0 0 R 0 0 R 0 0 0 R 19 0 0 R 11 18 1 1 R 10 17 0 0 R 9 16 1 1 R 8 CHIPID[15:8] VERSION[7:0] Chip ID register: bit description Symbol CHIPID[15:8] CHIPID[7:0] VERSION[7:0] Description Chip ID: Lower byte (15h) Chip ID: Upper byte (82h) Version: Version number (30h) 8.5.3 Frame Number register (address: 74h) This read-only register contains the frame number of the last successfully received Start-Of-Frame (SOF). The register contains 2 bytes, and the bit allocation is given in Table 65. In case of 8-bit access, the register content is returned lower byte first. Table 65. Bit Symbol Reset Bus reset Access Bit Symbol Reset Bus reset Access 0 0 R 0 0 R 0 0 R 0 0 R 7 Frame Number register: bit allocation 15 reserved 6 0 0 R 5 14 13 12 MICROSOF[2:0] 0 0 R 4 SOFR[7:0] 0 0 R 0 0 R 0 0 R 0 0 R 0 0 R 3 0 0 R 2 11 10 9 SOFR[10:8] 0 0 R 1 0 0 R 0 8 ISP1582_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 46 of 68 NXP Semiconductors ISP1582 Hi-Speed USB peripheral controller Frame Number register: bit description Symbol MICROSOF[2:0] SOFR[10:0] Description reserved microframe number frame number Table 66. Bit 15 to 14 13 to 11 10 to 0 8.5.4 Scratch register (address: 78h) This 16-bit register can be used by the firmware to save and restore information. For example, the device status before it enters the suspend state. The bit allocation is given in Table 67. Table 67. Bit Symbol Reset Bus reset Access Bit Symbol Reset Bus reset Access 0 0 R/W 0 0 R/W Table 68. Bit 15 to 8 7 to 0 0 0 R/W 0 0 R/W 0 0 R/W 7 0 0 R/W 6 0 0 R/W 5 0 0 R/W 4 SFIRL[7:0] 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W Scratch register: bit allocation 15 14 13 12 SFIRH[7:0] 0 0 R/W 3 0 0 R/W 2 0 0 R/W 1 0 0 R/W 0 11 10 9 8 Scratch register: bit description Symbol SFIRH[7:0] SFIRL[7:0] Description Scratch firmware information register (higher byte) Scratch firmware information register (lower byte) 8.5.5 Unlock Device register (address: 7Ch) To protect registers from getting corrupted when the ISP1582 goes into suspend, the write operation is disabled if bit PWRON in the Mode register is set to logic 0. In this case, when the chip resumes, the Unlock Device command must first be issued to this register before attempting to write to the rest of the registers. This is done by writing unlock code (AA37h) to this register. The bit allocation of the Unlock Device register is given in Table 69. Table 69. Bit Symbol Reset Bus reset Access Bit Symbol W 7 W 6 W 5 Unlock Device register: bit allocation 15 14 13 12 11 10 9 8 ULCODE[15:8] = AAh not applicable not applicable W 4 W 3 W 2 W 1 W 0 ULCODE[7:0] = 37h ISP1582_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 47 of 68 NXP Semiconductors ISP1582 Hi-Speed USB peripheral controller 6 5 4 3 2 1 0 Bit Reset Bus reset Access 7 not applicable not applicable W W Table 70. Bit 15 to 0 W W W W W W Unlock Device register: bit description Symbol ULCODE[15:0] Description Unlock Code: Writing data AA37h unlocks the internal registers and FIFOs for writing, following a resume. When bit PWRON in the Mode register is logic 1, the chip is powered. In such a case, you do not need to issue the Unlock command because the microprocessor is powered and therefore, the RD_N, WR_N and CS_N signals maintain their states. When bit PWRON is logic 0, the RD_N, WR_N and CS_N signals are floating because the microprocessor is not powered. To protect the ISP1582 registers from being corrupted during suspend, register write is locked when the chip goes into suspend. Therefore, you need to issue the Unlock command to unlock the ISP1582 registers. 8.5.6 Test Mode register (address: 84h) This 1-byte register allows the firmware to set pins DP and DM to predetermined states for testing purposes. The bit allocation is given in Table 71. Remark: Only one bit can be set to logic 1 at a time. This must be implemented for the Hi-Speed USB logo compliance testing. To exit test mode, power cycle is required. Table 71. Bit Symbol Reset Bus reset Access Test Mode register: bit allocation 7 FORCEHS 0 unchanged R/W Table 72. Bit 7 6 to 5 4 3 2 1 0 [1] [2] ISP1582_7 6 reserved - 5 - 4 FORCEFS 0 unchanged R/W 3 PRBS 0 0 R/W 2 KSTATE 0 0 R/W 1 JSTATE 0 0 R/W 0 SE0_NAK 0 0 R/W Test Mode register: bit description Description Force High-Speed: Logic 1[1] forces the hardware to high-speed mode only and disables the chirp detection logic. reserved Force Full-Speed: Logic 1[1] forces the physical layer to full-speed mode only and disables the chirp detection logic. Predetermined Random Pattern: Logic 1[2] sets pins DP and DM to toggle in a predetermined random pattern. K-State: Logic 1[2] sets pins DP and DM to the K state. J-State: Logic 1[2] sets pins DP and DM to the J state. SE0 NAK: Logic 1[2] sets pins DP and DM to a high-speed quiescent state. The device only responds to a valid high-speed IN token with a NAK. Symbol FORCEHS FORCEFS PRBS KSTATE JSTATE SE0_NAK Either FORCEHS or FORCEFS must be set at a time. Of the four bits (PRBS, KSTATE, JSTATE and SE0_NAK), only one bit must be set at a time. (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 48 of 68 NXP Semiconductors ISP1582 Hi-Speed USB peripheral controller 9. Limiting values Table 73. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VCC VCC(I/O) VI Ilu Vesd Tstg [1] Parameter supply voltage input/output supply voltage input voltage latch-up current electrostatic discharge voltage storage temperature Conditions Min -0.5 -0.5 [1] Max +4.6 +4.6 VCC + 0.5 100 +2000 +125 Unit V V V mA V C -0.5 -2000 -40 VI < 0 V or VI > VCC ILI < 1 A The maximum value for 5 V tolerant pins is 6 V. 10. Recommended operating conditions Table 74. Symbol VCC VCC(I/O) VI VIA(I/O) V(pu)OD Tamb Tj Recommended operating conditions Parameter supply voltage input/output supply voltage input voltage input voltage on analog I/O pins open-drain pull-up voltage ambient temperature junction temperature VCC = 3.3 V on pins DP and DM Conditions Min 3.0 VCC 0 0 0 -40 -40 Typ Max 3.6 VCC 3.3 3.6 VCC +85 +125 Unit V V V V V C C 11. Static characteristics Table 75. Static characteristics: supply pins VCC = 3.3 V 0.3 V; VGND = 0 V; Tamb = -40 C to +85 C; typical values at Tamb = 25 C; unless otherwise specified. Symbol VCC ICC Parameter supply voltage supply current VCC = 3.3 V high-speed full-speed ICC(susp) VCC(I/O) ICC(I/O) VCC(1V8) [1] Conditions Min 3.0 VCC [1] Typ 3.3 45 17 160 VCC 3 1.8 Max 3.6 60 25 VCC 1.95 Unit V mA mA A V mA V Supply voltage suspend supply current input/output supply voltage supply current on pin VCC(I/O) supply voltage (1.8 V) VCC = 3.3 V I/O pad supply voltage 1.65 Regulated supply voltage with voltage converter ICC(I/O) test condition: device set up under the test mode vector and I/O is subjected to external conditions. ISP1582_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 49 of 68 NXP Semiconductors ISP1582 Hi-Speed USB peripheral controller Table 76. Static characteristics: digital pins VCC(I/O) = VCC; VGND = 0 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol Input levels VIL VIH VOL VOH ILI [1] Parameter LOW-level input voltage HIGH-level input voltage LOW-level output voltage HIGH-level output voltage input leakage current Conditions Min - Typ - Max 0.3VCC(I/O) - Unit V V 0.7VCC(I/O) IOL = rated drive IOH = rated drive [1] Output levels 0.15VCC(I/O) V +5 V A 0.8VCC(I/O) -5 - Leakage current This value is applicable to transistor input only. The value will be different if internal pull-up or pull-down resistors are used. Table 77. Static characteristics: OTG detection VCC(I/O) = VCC; VGND = 0 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol RDN(VBUS) RUP(DP) Parameter pull-down resistance on pin VBUS pull-up resistance on pin DP Conditions only when bit DISCV is set in the OTG register only when bit DP is set in the OTG register Min 680 300 Typ 800 550 Max 1030 780 Unit Charging and discharging resistor Comparator levels VBVALID VSESEND VBUS valid detection VBUS B-session end detection 2.0 0.2 4.0 0.8 V V Table 78. Static characteristics: analog I/O pins DP and DM VCC = 3.3 V 0.3 V; VGND = 0 V; Tamb = -40 C to +85 C; unless otherwise specified.[1] Symbol Input levels VDI VCM VSE VIL VIH Vth(LH) Vth(HL) Vhys VOL VOH ILZ ISP1582_7 Parameter Conditions Min 0.2 0.8 0.8 2.0 1.4 0.9 0.4 Typ - Max 2.5 2.0 0.8 1.9 1.5 0.7 0.4 3.6 +10 Unit V V V V V V V V V V A differential input sensitivity voltage |VI(DP) - VI(DM)| differential common mode voltage range single-ended receiver threshold LOW-level input voltage HIGH-level input voltage positive-going threshold voltage negative-going threshold voltage hysteresis voltage LOW-level output voltage HIGH-level output voltage OFF-state leakage current RL = 1.5 k to 3.6 V RL = 15 k to GND 0 V < VI < 3.3 V includes VDI range Schmitt-trigger inputs Output levels 2.8 -10 Leakage current (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 50 of 68 NXP Semiconductors ISP1582 Hi-Speed USB peripheral controller Table 78. Static characteristics: analog I/O pins DP and DM ...continued VCC = 3.3 V 0.3 V; VGND = 0 V; Tamb = -40 C to +85 C; unless otherwise specified.[1] Symbol Cin Resistance ZDRV ZINP driver output impedance for driver which is not high-speed capable input impedance exclusive of pull-up/pull-down (for low-/full-speed) steady-state drive 40.5 10 49.5 M Parameter input capacitance Conditions pin to GND Min Typ Max 10 Unit pF Capacitance [1] Pin DP is the USB positive data pin, and pin DM is the USB negative data pin. 12. Dynamic characteristics Table 79. Dynamic characteristics VCC = 3.3 V 0.3 V; VGND = 0 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol Reset tW(RESET_N) fXTAL1 RS CL VI tJ tr tf external RESET_N pulse width crystal oscillator running frequency on pin XTAL1 series resistance load capacitance input voltage external clock jitter clock duty cycle rise time fall time 500 1.65 45 12 18 1.8 50 100 1.95 500 55 3 3 s MHz pF V ps % ns ns Crystal oscillator Parameter Conditions Min Typ Max Unit External clock input Table 80. Dynamic characteristics: analog I/O pins DP and DM VCC = 3.3 V 0.3 V; VGND = 0 V; Tamb = -40 C to +85 C; CL = 50 pF; RPU = 1.5 k on DP to VTERM; test circuit of Figure 23; unless otherwise specified. Symbol Parameter Driver characteristics Full-speed mode tFR tFF FRFM VCRS tHSR ISP1582_7 Conditions Min Typ Max Unit rise time fall time differential rise time/fall time matching output signal crossover voltage rise time (10 % to 90 %) CL = 50 pF; 10 % to 90 % of |VOH - VOL| CL = 50 pF; 90 % to 10 % of |VOH - VOL| tFR/tFF [1] 4 4 90 1.3 500 - 20 20 ns ns 111.11 % 2.0 V ps 51 of 68 [1][2] High-speed mode with captive cable Rev. 07 -- 22 September 2008 (c) NXP B.V. 2008. All rights reserved. Product data sheet NXP Semiconductors ISP1582 Hi-Speed USB peripheral controller Table 80. Dynamic characteristics: analog I/O pins DP and DM ...continued VCC = 3.3 V 0.3 V; VGND = 0 V; Tamb = -40 C to +85 C; CL = 50 pF; RPU = 1.5 k on DP to VTERM; test circuit of Figure 23; unless otherwise specified. Symbol Parameter tHSF fall time (10 % to 90 %) Data source timing Full-speed mode tFEOPT tFDEOP source SE0 interval of EOP source jitter for differential transition to SE0 transition see Figure 13 see Figure 13 [2] [2] Conditions with captive cable Min 500 Typ - Max - Unit ps 160 -2 - 175 +5 ns ns Receiver timing Full-speed mode tJR1 tJR2 tFEOPR tFST receiver jitter to next transition receiver SE0 interval of EOP width of SE0 interval during differential transition see Figure 14 accepted as EOP; see Figure 13 rejected as EOP; see Figure 15 [2] [2] [2] [2] -18.5 -9 82 - - +18.5 +9 14 ns ns ns ns receiver jitter for paired transitions see Figure 14 [1] [2] Excluding the first transition from the idle state. Characterized only, not tested. Limits guaranteed by design. TPERIOD +3.3 V crossover point differential data lines crossover point extended 0V differential data to SE0/EOP skew N x TPERIOD + t DEOP source EOP width: t EOPT receiver EOP width: t EOPR mgr776 TPERIOD is the bit duration corresponding to the USB data rate. Full-speed timing symbols have a subscript prefix `F', low-speed timing symbols have a prefix 'L'. Fig 13. Source differential data-to-EOP transition skew and EOP width ISP1582_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 52 of 68 NXP Semiconductors ISP1582 Hi-Speed USB peripheral controller TPERIOD +3.3 V differential data lines 0V t JR consecutive transitions N x TPERIOD + t JR1 paired transitions N x TPERIOD + t JR2 t JR1 t JR2 mgr871 TPERIOD is the bit duration corresponding to the USB data rate. Fig 14. Receiver differential data jitter t FST +3.3 V differential data lines VIH(min) 0V mgr872 Fig 15. Receiver SE0 width tolerance 12.1 Register access timing Table 81. Register access timing parameters: separate address and data buses VCC(I/O) = VCC = 3.3 V; VGND = 0 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol Reading tRLRH tAVRL tRHAX tRLDV tRHDZ tRHSH tSLRL Writing tWLWH tAVWL tWHAX tDVWH tWHDZ ISP1582_7 Parameter RD_N LOW pulse width address set-up time before RD_N LOW address hold time after RD_N HIGH RD_N LOW to data valid delay RD_N HIGH to data outputs three-state delay RD_N HIGH to CS_N HIGH delay CS_N LOW to RD_N LOW delay WR_N LOW pulse width address set-up time before WR_N LOW address hold time after WR_N HIGH data set-up time before WR_N HIGH data hold time after WR_N HIGH Conditions Min > tRLDV 0 0 0 0 2 15 0 0 11 5 Typ - Max 26 15 - Unit ns ns ns ns ns ns ns ns ns ns ns ns (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 53 of 68 NXP Semiconductors ISP1582 Hi-Speed USB peripheral controller Table 81. Register access timing parameters: separate address and data buses ...continued VCC(I/O) = VCC = 3.3 V; VGND = 0 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol tWHSH tSLWL General Tcy(RW) tWHRL read or write cycle time WR_N HIGH to RD_N LOW time 50 91 ns ns Parameter WR_N HIGH to CS_N HIGH delay CS_N LOW to WR_N LOW delay Conditions Min 0 2 Typ Max Unit ns ns Tcy(RW) tWHSH tSLWL CS_N tSLRL tWHAX tRHAX tRHSH A[7:0] tRLDV (read) DATA[15:0] tRHDZ tAVRL RD_N tRLRH tAVWL (write) DATA[15:0] tDVWH WR_N tWLWH tWHDZ 004aaa276 Fig 16. Register access timing: separate address and data buses WR_N RD_N tWHRL 004aab064 Applies only to write followed by read to the same or different registers. Fig 17. ISP1582 ready signal timing ISP1582_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 54 of 68 NXP Semiconductors ISP1582 Hi-Speed USB peripheral controller 12.2 DMA timing Table 82. GDMA mode timing parameters VCC(I/O) = VCC = 3.3 V; VGND = 0 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol Tcy1 tsu1 td1 th1 tw1 tw2 td2 th2 th3 tsu2 tsu3 ta1 Parameter read or write cycle time DREQ set-up time before first DACK on DREQ on delay after last strobe off DREQ hold time after last strobe on DIOR or DIOW pulse width DIOR/DIOW recovery time read data valid delay after strobe on read data hold time after strobe off write data hold time after strobe off write data set-up time before strobe off DACK set-up time before DIOR/DIOW assertion DACK deassertion after DIOR/DIOW deassertion Conditions Min 75 10 33.33 0 39 36 1 10 0 0 Typ Max 53 600 20 5 30 Unit ns ns ns ns ns ns ns ns ns ns ns ns DREQ(2) tsu1 tw1 DACK(1) tsu3 DIOR or DIOW(1) td2 (read) DATA[15:0] tsu2 (write) DATA[15:0] mgt500 Tcy1 th1 td1 tw2 th2 ta1 th3 DREQ is continuously asserted, until the last transfer is done or the FIFO is full. Data strobes: DIOR (read) and DIOW (write). (1) Programmable polarity: shown as active LOW. (2) Programmable polarity: shown as active HIGH. Fig 18. GDMA mode timing (bits MODE[1:0] = 00) ISP1582_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 55 of 68 NXP Semiconductors ISP1582 Hi-Speed USB peripheral controller DREQ(2) tsu3 tw1 Tcy1 td1 th1 tsu1 DACK(1) td2 DIOR or DIOW(1) th2 ta1 (read) DATA[15:0] tsu2 th3 (write) DATA[15:0] mgt502 DREQ is asserted for every transfer. Data strobes: DIOR (read) and DACK (write). (1) Programmable polarity: shown as active LOW. (2) Programmable polarity: shown as active HIGH. Fig 19. GDMA mode timing (bits MODE[1:0] = 01) DREQ(2) tsu1 DACK(1) td2 HIGH th2 (read) DATA[15:0] tsu2 (write) DATA[15:0] mgt501 tw1 Tcy1 th1 tw2 td1 DIOR or DIOW(1) th3 DREQ is continuously asserted, until the last transfer is done or the FIFO is full. Data strobe: DACK (read/write). (1) Programmable polarity: shown as active LOW. (2) Programmable polarity: shown as active HIGH. Fig 20. GDMA mode timing (bits MODE[1:0] = 10) ISP1582_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 56 of 68 NXP Semiconductors ISP1582 Hi-Speed USB peripheral controller RW_N or WR_N 36 ns (min) EOT(1) DREQ th1 004aaa928 (1) Programmable polarity: shown as active LOW. Remark: EOT must be valid for 36 ns (minimum) when RD_N or WR_N is active. Fig 21. EOT timing in generic processor mode 13. Application information address data CPU 8 ISP1582 A[7:0] 16 DATA[15:0] read strobe write strobe chip select RD_N WR_N CS_N 004aaa206 Fig 22. Typical interface connections for generic processor mode 14. Test information The dynamic characteristics of the analog I/O ports DP and DM were determined using the circuit shown in Figure 23. test point DUT 15 k CL 50 pF mgt495 In full-speed mode, an internal 1.5 k pull-up resistor is connected to pin DP. Fig 23. Load impedance for pins DP and DM (full-speed mode) ISP1582_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 57 of 68 NXP Semiconductors ISP1582 Hi-Speed USB peripheral controller 15. Package outline HVQFN56: plastic thermal enhanced very thin quad flat package; no leads; 56 terminals; body 8 x 8 x 0.85 mm SOT684-1 D B A terminal 1 index area E A A1 c detail X e1 e 15 L 14 1/2 e C b 28 29 e vMCAB wMC y1 C y Eh 1/2 e e2 1 terminal 1 index area 56 Dh 0 DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D(1) 8.1 7.9 Dh 4.45 4.15 E(1) 8.1 7.9 Eh 4.45 4.15 e 0.5 43 42 X 2.5 scale e1 6.5 e2 6.5 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1 5 mm Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT684-1 REFERENCES IEC --JEDEC MO-220 JEITA --EUROPEAN PROJECTION ISSUE DATE 01-08-08 02-10-22 Fig 24. Package outline SOT684-1 (HVQFN56) ISP1582_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 58 of 68 NXP Semiconductors ISP1582 Hi-Speed USB peripheral controller 16. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description". 16.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 16.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: * Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: * * * * * * Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 16.3 Wave soldering Key characteristics in wave soldering are: * Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave * Solder bath specifications, including temperature and impurities ISP1582_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 59 of 68 NXP Semiconductors ISP1582 Hi-Speed USB peripheral controller 16.4 Reflow soldering Key characteristics in reflow soldering are: * Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 25) than a SnPb process, thus reducing the process window * Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board * Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 83 and 84 Table 83. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 84. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 350 220 220 Package thickness (mm) Package thickness (mm) Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 25. ISP1582_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 60 of 68 NXP Semiconductors ISP1582 Hi-Speed USB peripheral controller temperature maximum peak temperature = MSL limit, damage level minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 25. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description". 17. Abbreviations Table 85. Acronym ACK ACPI ASIC CRC DMA EMI ESR FS GDMA HS MMU NAK NRZI NYET OTG PCB PHY PID PIE ISP1582_7 Abbreviations Description Acknowledgement Advanced Configuration and Power Interface Application-Specific Integrated Circuit Cyclic Redundancy Code Direct Memory Access ElectroMagnetic Interference Equivalent Series Resistance Full-Speed Generic DMA High-Speed Memory Management Unit Not Acknowledged Non-Return-to-Zero Inverted Not Yet On-The-Go Printed-Circuit Board Physical Packet IDentifier Parallel Interface Engine (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 61 of 68 NXP Semiconductors ISP1582 Hi-Speed USB peripheral controller Abbreviations ...continued Description Parallel Input/Output Phase-Locked Loop Power-On Reset Receive Single-Ended zero Serial Interface Engine Session Request Protocol Transistor-Transistor Logic Transmit Universal Serial Bus Table 85. Acronym PIO PLL POR RX SE0 SIE SRP TTL TX USB 18. References [1] [2] [3] [4] Universal Serial Bus Specification Rev. 2.0 On-The-Go Supplement to the USB Specification Rev. 1.3 Using ISP1582/3 in a composite device application with alternate settings (AN10071) ISP1582/83 and ISP1761 clearing an IN buffer (AN10045) ISP1582_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 62 of 68 NXP Semiconductors ISP1582 Hi-Speed USB peripheral controller 19. Revision history Table 86. ISP1582_7 Modifications: Revision history Release date 20080922 Data sheet status Product data sheet Change notice Supersedes ISP1582_6 Document ID * * * * * * * * * * * * * * * Added Table 3 "Endpoint access and programmability". Removed Section 7.9 "Clear buffer". Table 4 "ISP1582 pin status": updated. Table 5 "ISP1582 output status": removed two rows. Section 7.15 "Power supply": updated. Figure 12 "Bus-powered mode": updated. Table 18 "Mode register: bit allocation": updated the bus reset value for bits CLKAON and PWRON. Table 28 "Endpoint Index register: bit allocation": updated the reset and bus reset values for bit EP0SETUP. Table 32 "Control Function register: bit description": updated description for bit CLBUF. Section 8.3.6 "Endpoint MaxPacketSize register (address: 04h)": updated the first paragraph. Table 42 "Endpoint Type register: bit description": added a remark to the DBLBUF description. Table 46 "DMA commands": added a remark to the GDMA stop. Section 12.1 "Register access timing": updated. Figure 18 "GDMA mode timing (bits MODE[1:0] = 00)": updated. Section 18 "References": updated Ref. 3. Product data sheet Product data sheet Product data Preliminary data Preliminary data Preliminary data 200412038 ISP1582_5 ISP1582-04 ISP1582-03 ISP1582-02 ISP1582-01 - ISP1582_6 ISP1582_5 ISP1582-04 (9397 750 14033) ISP1582-03 (9397 750 13699) ISP1582-02 (9397 750 12979) ISP1582-01 (9397 750 11496) 20070920 20070201 20050104 20040825 20040629 20040223 ISP1582_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 63 of 68 NXP Semiconductors ISP1582 Hi-Speed USB peripheral controller 20. Legal information 20.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 20.2 Definitions Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 20.3 Disclaimers General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected 20.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. SoftConnect -- is a trademark of NXP B.V. 21. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com ISP1582_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 64 of 68 NXP Semiconductors ISP1582 Hi-Speed USB peripheral controller 22. Tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Table 49. ISP1582_7 Ordering information . . . . . . . . . . . . . . . . . . . . .2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .4 Endpoint access and programmability . . . . . . . .8 ISP1582 pin status . . . . . . . . . . . . . . . . . . . . . .11 ISP1582 output status . . . . . . . . . . . . . . . . . . .12 Power modes . . . . . . . . . . . . . . . . . . . . . . . . . .17 Operation truth table for SoftConnect . . . . . . .18 Operation truth table for clock off during suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Operation truth table for back voltage compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Operation truth table for OTG . . . . . . . . . . . . .19 Operation truth table for SoftConnect . . . . . . .19 Operation truth table for clock off during suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Operation truth table for back voltage compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Operation truth table for OTG . . . . . . . . . . . . .20 Register overview . . . . . . . . . . . . . . . . . . . . . .21 Address register: bit allocation . . . . . . . . . . . .23 Address register: bit description . . . . . . . . . . .23 Mode register: bit allocation . . . . . . . . . . . . . . .23 Mode register: bit description . . . . . . . . . . . . .23 Status of the chip . . . . . . . . . . . . . . . . . . . . . . .24 Interrupt Configuration register: bit allocation .25 Interrupt Configuration register: bit description 25 Debug mode settings . . . . . . . . . . . . . . . . . . . .25 OTG register: bit allocation . . . . . . . . . . . . . . .25 OTG register: bit description . . . . . . . . . . . . . .26 Interrupt Enable register: bit allocation . . . . . .28 Interrupt Enable register: bit description . . . . .28 Endpoint Index register: bit allocation . . . . . . .29 Endpoint Index register: bit description . . . . . .30 Addressing of endpoint buffers . . . . . . . . . . . .30 Control Function register: bit allocation . . . . . .30 Control Function register: bit description . . . . .31 Data Port register: bit allocation . . . . . . . . . . .32 Data Port register: bit description . . . . . . . . . .32 Buffer Length register: bit allocation . . . . . . . .33 Buffer Length register: bit description . . . . . . .33 Buffer Status register: bit allocation . . . . . . . . .34 Buffer Status register: bit description . . . . . . . .34 Endpoint MaxPacketSize register: bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Endpoint MaxPacketSize register: bit description . . . . . . . . . . . . . . . . . . . . . . . . .35 Endpoint Type register: bit allocation . . . . . . . .35 Endpoint Type register: bit description . . . . . . .36 Control bits for GDMA read/write (opcode = 00h/01h) . . . . . . . . . . . . . . . . . . . . .37 DMA Command register: bit allocation . . . . . .37 DMA Command register: bit description . . . . .37 DMA commands . . . . . . . . . . . . . . . . . . . . . . .38 DMA Transfer Counter register: bit allocation .38 DMA Transfer Counter register: bit description 39 DMA Configuration register: bit allocation . . . .39 Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. DMA Configuration register: bit description . . . 40 DMA Hardware register: bit allocation . . . . . . . 40 DMA Hardware register: bit description . . . . . 41 DMA Interrupt Reason register: bit allocation . 41 DMA Interrupt Reason register: bit description 42 Internal EOT-functional relation with bit DMA_XFER_OK . . . . . . . . . . . . . . . . . . . . . . . 42 DMA Interrupt Enable register: bit allocation . . 42 DMA Endpoint register: bit allocation . . . . . . . 43 DMA Endpoint register: bit description . . . . . . 43 DMA Burst Counter register: bit allocation . . . 43 DMA Burst Counter register: bit description . . 44 Interrupt register: bit allocation . . . . . . . . . . . . 44 Interrupt register: bit description . . . . . . . . . . . 45 Chip ID register: bit allocation . . . . . . . . . . . . . 46 Chip ID register: bit description . . . . . . . . . . . . 46 Frame Number register: bit allocation . . . . . . . 46 Frame Number register: bit description . . . . . . 47 Scratch register: bit allocation . . . . . . . . . . . . . 47 Scratch register: bit description . . . . . . . . . . . . 47 Unlock Device register: bit allocation . . . . . . . 47 Unlock Device register: bit description . . . . . . 48 Test Mode register: bit allocation . . . . . . . . . . . 48 Test Mode register: bit description . . . . . . . . . 48 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . 49 Recommended operating conditions . . . . . . . . 49 Static characteristics: supply pins . . . . . . . . . . 49 Static characteristics: digital pins . . . . . . . . . . 50 Static characteristics: OTG detection . . . . . . . 50 Static characteristics: analog I/O pins DP and DM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Dynamic characteristics . . . . . . . . . . . . . . . . . 51 Dynamic characteristics: analog I/O pins DP and DM . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Register access timing parameters: separate address and data buses . . . . . . . . . . 53 GDMA mode timing parameters . . . . . . . . . . . 55 SnPb eutectic process (from J-STD-020C) . . . 60 Lead-free process (from J-STD-020C) . . . . . . 60 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 63 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 65 of 68 NXP Semiconductors ISP1582 Hi-Speed USB peripheral controller 23. Figures Fig 1. Fig 2. Fig 3. Fig 4. Fig 5. Fig 6. Fig 7. Fig 8. Fig 9. Fig 10. Fig 11. Fig 12. Fig 13. Fig 14. Fig 15. Fig 16. Fig 17. Fig 18. Fig 19. Fig 20. Fig 21. Fig 22. Fig 23. Fig 24. Fig 25. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Pin configuration HVQFN56 (top view) . . . . . . . . .4 Interrupt logic . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Behavior of bit GLINTENA . . . . . . . . . . . . . . . . . .14 Resistor and electrolytic or tantalum capacitor needed for VBUS sensing . . . . . . . . . . . . . . . . . . .15 Oscilloscope reading: no resistor and capacitor in the network . . . . . . . . . . . . . . . . . . . .15 Oscilloscope reading: with resistor and capacitor in the network . . . . . . . . . . . . . . . . . . . .15 POR timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Clock with respect to the external POR . . . . . . . .16 ISP1582 with 3.3 V supply . . . . . . . . . . . . . . . . . .17 Self-powered mode . . . . . . . . . . . . . . . . . . . . . . .18 Bus-powered mode . . . . . . . . . . . . . . . . . . . . . . .19 Source differential data-to-EOP transition skew and EOP width . . . . . . . . . . . . . . . . . . . . . .52 Receiver differential data jitter . . . . . . . . . . . . . . .53 Receiver SE0 width tolerance . . . . . . . . . . . . . . .53 Register access timing: separate address and data buses . . . . . . . . . . . . . . . . . . . . . . . . . .54 ISP1582 ready signal timing . . . . . . . . . . . . . . . .54 GDMA mode timing (bits MODE[1:0] = 00) . . . . .55 GDMA mode timing (bits MODE[1:0] = 01) . . . . .56 GDMA mode timing (bits MODE[1:0] = 10) . . . . .56 EOT timing in generic processor mode . . . . . . . .57 Typical interface connections for generic processor mode . . . . . . . . . . . . . . . . . . . . . . . . . .57 Load impedance for pins DP and DM (full-speed mode) . . . . . . . . . . . . . . . . . . . . . . . . .57 Package outline SOT684-1 (HVQFN56) . . . . . . .58 Temperature profiles for large and small components . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 ISP1582_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 66 of 68 NXP Semiconductors ISP1582 Hi-Speed USB peripheral controller 24. Contents 1 2 3 4 5 6 6.1 6.2 7 7.1 7.2 7.3 7.4 7.5 7.6 7.6.1 7.6.2 7.6.3 7.6.4 7.7 7.8 7.9 7.10 7.11 7.12 7.12.1 7.12.2 7.13 7.14 7.15 7.15.1 7.15.2 8 8.1 8.2 8.2.1 8.2.2 8.2.3 8.2.4 8.2.4.1 8.2.5 8.3 8.3.1 8.3.2 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 8 DMA interface, DMA handler and DMA registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Hi-Speed USB transceiver . . . . . . . . . . . . . . . . 9 MMU and integrated RAM . . . . . . . . . . . . . . . . 9 Microcontroller interface and microcontroller handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 OTG SRP module . . . . . . . . . . . . . . . . . . . . . . . 9 NXP high-speed transceiver . . . . . . . . . . . . . . 10 NXP Parallel Interface Engine (PIE) . . . . . . . . 10 Peripheral circuit . . . . . . . . . . . . . . . . . . . . . . . 10 HS detection . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 NXP Serial Interface Engine (SIE) . . . . . . . . . 11 SoftConnect . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Reconfiguring endpoints . . . . . . . . . . . . . . . . . 11 System controller . . . . . . . . . . . . . . . . . . . . . . 11 Pins status . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Interrupt output pin . . . . . . . . . . . . . . . . . . . . . 12 Interrupt control . . . . . . . . . . . . . . . . . . . . . . . 14 VBUS sensing . . . . . . . . . . . . . . . . . . . . . . . . . 14 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 15 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . 16 Self-powered mode. . . . . . . . . . . . . . . . . . . . . 18 Bus-powered mode. . . . . . . . . . . . . . . . . . . . . 19 Register description . . . . . . . . . . . . . . . . . . . . 21 Register access . . . . . . . . . . . . . . . . . . . . . . . 22 Initialization registers . . . . . . . . . . . . . . . . . . . 22 Address register (address: 00h) . . . . . . . . . . . 22 Mode register (address: 0Ch) . . . . . . . . . . . . . 23 Interrupt Configuration register (address: 10h) 24 OTG register (address: 12h) . . . . . . . . . . . . . . 25 Session Request Protocol (SRP) . . . . . . . . . . 27 Interrupt Enable register (address: 14h) . . . . . 27 Data flow registers . . . . . . . . . . . . . . . . . . . . . 29 Endpoint Index register (address: 2Ch) . . . . . 29 Control Function register (address: 28h) . . . . 30 8.3.3 8.3.4 8.3.5 8.3.6 8.3.7 8.4 8.4.1 8.4.2 8.4.3 8.4.4 8.4.5 8.4.6 8.4.7 8.4.8 8.5 8.5.1 8.5.2 8.5.3 8.5.4 8.5.5 8.5.6 9 10 11 12 12.1 12.2 13 14 15 16 16.1 16.2 16.3 16.4 17 18 19 20 20.1 20.2 20.3 20.4 21 Data Port register (address: 20h) . . . . . . . . . . Buffer Length register (address: 1Ch) . . . . . . Buffer Status register (address: 1Eh) . . . . . . . Endpoint MaxPacketSize register (address: 04h) . . . . . . . . . . . . . . . . . . . . . . . . Endpoint Type register (address: 08h) . . . . . . DMA registers . . . . . . . . . . . . . . . . . . . . . . . . DMA Command register (address: 30h) . . . . DMA Transfer Counter register (address: 34h) DMA Configuration register (address: 38h) . . DMA Hardware register (address: 3Ch) . . . . . DMA Interrupt Reason register (address: 50h) DMA Interrupt Enable register (address: 54h) DMA Endpoint register (address: 58h). . . . . . DMA Burst Counter register (address: 64h). . General registers . . . . . . . . . . . . . . . . . . . . . . Interrupt register (address: 18h). . . . . . . . . . . Chip ID register (address: 70h) . . . . . . . . . . . Frame Number register (address: 74h) . . . . . Scratch register (address: 78h) . . . . . . . . . . . Unlock Device register (address: 7Ch). . . . . . Test Mode register (address: 84h) . . . . . . . . . Limiting values . . . . . . . . . . . . . . . . . . . . . . . . Recommended operating conditions . . . . . . Static characteristics . . . . . . . . . . . . . . . . . . . Dynamic characteristics . . . . . . . . . . . . . . . . . Register access timing . . . . . . . . . . . . . . . . . . DMA timing. . . . . . . . . . . . . . . . . . . . . . . . . . . Application information . . . . . . . . . . . . . . . . . Test information. . . . . . . . . . . . . . . . . . . . . . . . Package outline . . . . . . . . . . . . . . . . . . . . . . . . Soldering of SMD packages . . . . . . . . . . . . . . Introduction to soldering. . . . . . . . . . . . . . . . . Wave and reflow soldering . . . . . . . . . . . . . . . Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . 31 32 33 34 35 36 37 38 39 40 41 42 43 43 44 44 46 46 47 47 48 49 49 49 51 53 55 57 57 58 59 59 59 59 60 61 62 63 64 64 64 64 64 64 continued >> ISP1582_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 67 of 68 NXP Semiconductors ISP1582 Hi-Speed USB peripheral controller 22 23 24 Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'. (c) NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 22 September 2008 Document identifier: ISP1582_7 |
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